10gb/s Design Of Low Power Clock Data Recovery Circuit

Clock and data recovery circuit is a very important circuit structure.It is mainly used in wire and fiber communication between fiber and metal.A general communication system is usually composed of a transmitting module,a channel and a receiving module.The signal received by the receiving module is usually a serial data stream.In order to meet the requirements of high-speed transmission,the current communication system usually includes the clock information into the data stream.The clock information is extracted from the data stream,and then the extracted clock signal is used to resample the data.The process of processing the signal is called the clock data recovery.The highest working speed of clock data recovery circuit limits the maximum transmission speed of communication system.By studying the technology of clock data recovery circuit,the design of a high speed and low power CDR circuit with a speed of lOGb/s is realized by using the principle of low power design.First,the typical circuit structure is analyzed,and the clock recovery circuit based on the two class of PLL is analyzed.By using typical system analysis,a theoretical model of circuit design is established,and the relationship between key parameters of circuit design is obtained.After comparing the relevant design indexes at home and abroad,the principle design of the circuit is finally completed.By establishing MATLAB model,the circuit bandwidth is 17MHz and the system is stable.Secondly,the design of phase detector in circuit is realized by using charge control technology and half rate technology.The half rate charge control phase detector has the advantages of low power,high speed and easy integration.Compared with the typical binary phase detector,the design can reduce the power consumption by about half.The design of VI conversion in the circuit is obtained by using the source level switch structure technology.The VI conversion has the characteristics of suppressing charge injection,reducing charge mismatch and high sensitivity.In the case of the standard loss ratio,the output voltage can reach 80%of the voltage range and meet the needs of the large part of the circuit.The four stage ring vibration structure and the common mode reconstruction technique are used to design the voltage controlled oscillator and the supporting buffer circuit.The K value of the oscillator at different process angles is in the range of 3.2GHz/V to 5.1 GHz/V when the output frequency is working frequency.The buffer can increase the output swing from forty percent to ninety percent,and at the same time,the duty cycle will be stabilized at fifty percent,which meets the design requirements.Then using the virtuoso layout tool to draw the layout of the design,through the planning of the key paths,inter module interaction line planning,module protection method to get the overall layout of the design.Finally,the simulation of clock data recovery circuit is carried out by using the simulation tool of virtuoso software.The operating frequency of the circuit to 5GHz belongs to high speed design,the processing speed of data reaches 10Gb/s,the maximum jitter is 15ps under different PVT conditions,the power consumption is 7.5mA×0.9V,and the chip area is 170um×150um.The design of other CDR circuits with the same speed has obvious advantages of low power consumption and small area.Based on the research and analysis of the clock data recovery circuit,a low power consumption high speed CDR circuit is obtained.Compared with the traditional design,the design realized in this paper can achieve the same processing speed with only 1/10 of its power consumption.The research of this topic provides powerful data support for high speed and low power design of analog circuits,and makes some contributions to the design of clock data recovery circuit.