Design The Circuit And Layout Of LDO For The Anti-radiation DAC Chip

With the rapid development of aerospace technology,our country has paid more and more attention to the development of the space industry.Integrated circuits are the mainstay of space technology.How to ensure the reliability of integrated circuit in complex aerospace environments is a meaningful research field.Low-dropout linear regulators(LDOs)have become one of the most widely used power management circuits due to their superior performance such as low power consumption,high accuracy,and fast response.Therefore,it is very important to study LDO with high reliability and anti-radiation.The purpose of this paper is to design an output-capacitorless LDO,which is integrated in an anti-radiation digital-to-analog converter(DAC)chip to supply voltage for address decoding and data latch modules.Firstly,according to the requirements of the antiirradiation of the whole circuit,the effect mechanism of the total dose radiation effect on integrated circuits is analyzed in this paper,and the corresponding anti-irradiation methods is proposed to make the circuit meet the total dose irradiation requirement.This paper requires Anti-total dose radiation not lower than 100Krad(Si).In this paper,it is required that the stable output voltage of the LDO designed is 4.8V within a wide input range of 5V~6.3V and the minimum voltage drop is 200 m V.Because the LDO designed in this paper is used to supply voltage for the digital circuit.Not only must the output accuracy of the LDO be guaranteed,but also the load transient response of the circuit have to be very excellent.The load transient response of the traditional LDO and the outputcapacitorless Low-dropout Regulators is compared in this paper,according to which the transient enhancement circuit suitable for this paper is proposed,combining the existing methods.The LDO designed in this paper is a three-level structure.The first stage is a folded cascode error amplifier,the second stage is a buffer,and the third stage is a PMOS power regulation tube.The frequency compensation method used in this paper is Nested Miller Compensation(NMC).Not only is the slew rate of the gate of the adjusting tube increased through the second-stage buffer,but also adds an additional transient boosting circuit is added to further improve the system's load transient response in this paper.The Dongbu Hi Tek BCD 0.18?m process is used to complete the design and simulation of each module of the circuit in this paper.When the power supply voltage is 5V,the load capacitance is 50 p F,and the temperature is 27 degrees centigrade,the simulation results are: the lowest voltage drop is 200 m V,and the maximum load is 100 m A,and the load regulation is 0.2493(?V/m A),and the linear adjustment rate of power voltage is 0.197(m V/V),the low frequency gain of the entire loop is 97 d B at least,and the phase margin of the system is 75 degrees at least,and the PSRR is 84 d B(100Hz)at least.When the current jumps from 2m A to 100 m A,the maximum overshoot voltage of the output is only 37.7m V.Finally,the layout of the whole circuit with the ring-gate MOSFET is completed.Overall,an outputcapacitorless Low-dropout Regulators designed in this paper meets the design requirements of this project.