The Study And Design Of Low-noise Low-power Sensor Read-out Integrated Circuits

Sensor read-out integrated circuits(ROICs)are used to convert the feeble analog output of the sensor to the digital form,and ROICs are widely applied in industry controlling,instrumentation,auxiliary analog-to-digital interface of micro-processors and so on.In this dissertation,a low-noise low-power ROIC for measurement of ultra-low-frequency signals was designed,and it consists of a low-noise instrumentation amplifier(IA)and an analog-to-digital convertor(ADC).The key and difficult point of this design is that the treatment methods of the low-frequency noise.The dissertation paid more attention on the research of theory of ROIC,architecture,noise analysis and circuits.The main work and achievements are presented as follows:1)Based on double-sampling technique,a new circuit architecture that the IA was embedded into the switched-capacitor integrator of the?-?modulator was proposed.Due to this architecture,the 1/f noise of the IA was reduced and the circuit was simplified,moreover,the external capacitor at the IA output is no longer needed and the pin number of the chip was reduced and the application cost was saved.2)The flow for the system design of low-frequency narrow-band?-?ADC was proposed,including the methods of designing the?-?modulators architecture,designing the noise transfer function and optimizing the coefficients of modulators.The optimized low-frequency narrow-band?-?ADC with low noise and low power consumption can be obtained by employing the proposed system design flow.3)The noise of CMOS circuit was deeply analyzed,and the narrow-band noise of the IA was optimized.Furthermore,the 1/f noise of the first stage switched-capacitor integrator of the?-?modulator was reduced by using correlated-double sampling technique.4)The digital decimation filter of the?-?ADC was described in verilog-HDL,synthesized,placed and routed automatically,which can operate at 10Hz or 80Hz data rate.When it operates at 10Hz,simultaneous rejection of 50Hz and 60Hz line noise was achieved.5)The circuits were implemented with UMC 0.11?m CMOS process and the supply of the chip was expanded from 2.7~5.5V to 1.7~5.5V compared with the most commercial products,which also extended the application range of the chip and the power consumption was reduced.After completed the circuit and layout design,the post-layout simulation was accomplished.The circuit and layout were implemented with UMC 0.11?m 2P6M CMOS process,and the full chip area including IO pad is 1.6×1.4 mm~2.The supply of the chip is 1.7~5.5V and a LDO circuit was employed to provide a 1.5V supply which was used by the other circuits.The full chip dissipated 2.3m A current and the maximum power consumption of the chip was 3.8m W.The post simulation results showed that the input-referred noise of the chip was12n V/rt(Hz),and the effective number of bits was 18.7-bits under 10Hz data rate.The expected objective is achieved.