High-speed,Low-power-dissipation,Small-area SAR ADC IP Design

System on chip(SOC)design requires all the blocks a good compatibility with each other,which means a smaller layout area,lower power dissipation and lower input capacitance load.Among all the ADC structures,successive approximation ADC(SAR ADC)has a wide application in SOC design because of its small layout area,low power dissipation.What's more,the absence of amplifier makes SAR ADC a better compatibility with process development.SAR ADC can achieve a good performance in high speed design even better than pipeline ADC in some advanced process.This paper proposed a 10 bit,100MS/s,low-power-dissipation,small-layout-area,low-input-capacitance SAR ADC IP core with an analog foreground capacitance mismatch calibration based on code density test in 65 nm CMOS process.Then this paper gives the results of MATLAB behavioral simulation,schematic simulation,layout post simulation and measurement,and optimizes the design based on the measurement results.Six chapters are included in this paper.Chapter 1 describes the project background and the ADC research status.Meanwhile,after analyzing the existing capacitance mismatch calibration techniques,this paper proposed an analog foreground capacitance mismatch calibration technique which is based on the code density test.The main structure of a traditional SAR ADC and the principle of the proposed capacitance mismatch calibration technique are described in Chapter 2.In Chapter 3,this paper gives a detailed description of the design and optimization of the main blocks of the proposed SAR ADC core including the comparator,DAC block,SAR logic block,the calibration digital logic block,the configurable capacitance block,the bus structure.Chapter 4 is the results of MATLAB behavioral simulation,schematic simulation and layout post simulation of the SAR ADC IP core.This design is fabricated in Tsmc65 nm GP process.Chapter 5 describes the simulation and measurement environment,and then gives the results of the measurement results under different conditions,which shows the capacitance calibration system can just work chip off.After analyzing the cause of this phenomenon,some optimizations are used in the next tape out version.After the chip off capacitance weight calibration,this chip can achieve an ENOB of 8.93 bit at low input frequency and 8.86 bit at Nequist,translating into an FOM of 23.2 fJ/conv-step,and the DNL is-0.64LSB/0.54 LSB,INL is-1.43 LSB /1.32 LSB at a low input frequency.This SAR ADC core occupies an area of 90um*97um with a input capacitance of 150 fF.