Research On On-Chip Temperature And Capacitance Measurement

With the rapid development of semiconductor industry, chips have much higher power and nonuniform distribution of temperature. In order to monitor hot spots of chips, the research of on-chip temperature measurement techniques becomes important. On-chip capacitance measurement which can be used to model the parasitic parameters of interconnects and monitor IC manufacturing is very useful in new technology node and much attention has been paid to it.CMOS smart temperature sensor is a kind of on-chip temperature measurement techniques. In order to reduce mismatch error and maintain high dynamic range, a novel CMOS smart temperature sensor which has fewer current mirrors and will switch between two operational modes is designed in0.18um CMOS technology. The simulation result and the chip testing result show that compared with traditional CMOS smart temperature sensor, the new structure has a dynamic range of about90%and can reduce more than66%of mismatch error within military temperature range.Charge-Based Capacitance Measurement (CBCM) is a high accuracy and simple on-chip capacitance measurement technique. Addressable CBCM test structure has high testing speed and compact layout. Some methods which can be used to reduce measurement error are introduced after the simulation and theoretical error analysis of CBCM basic test structure. The55nm and28nm chip testing results of addressable CBCM measurement structures are introduced in the end of this thesis. The tape-out, manufacture as well as the measurement of addressable CBCM structures represents the state-of-the-art in this area.