Research On Key Technology Of Low Power Short Distance Wireless Transceivers

Due to the extensive use of short-range wireless communication networks,wireless transceiver chips have huge market potential.In a typical application scenario,the communication between the gateway and the wireless node has significant characteristics.The transmitter works for a long time to transmit the data collected by the sensor,and the receiver receives the configuration information in a short time.Faced with such features,transmitters with high emission rate,very low power consumption and receivers with high cost performance are what we expect.Traditional wireless transceivers are limited by their own structure,it is difficult to break through the bottleneck of power consumption.Typically,wireless communication nodes are powered by battery with limited energy,which means that research on low-power wireless transceivers is more meaningful.On the basis of the existing low power consumption technology,two new transmitters with high emission rate and low power consumption,a cost-effective receiver are proposed and implemented.One of the two new transmitters,which eliminates the need for modules such as DACs,LPFs,and Mixers in conventiona l transmitters and achieves signal modulation and amplification directly on the switch-mode DPA array,uses 1bit??modulator and implantable FIR filter technology to reduce power consumption.In addition,to solve the problem of low emission rate of 1bit DSM transmitter limited by oversampling rate,another new transmitter is proposed based on injection locking and edge-combining technology.This transmitter using a reconfigurable power amplifier array,with a lower oversampling rate,can achieve a higher emission rate.At the same time,with the only PA module working at the carrier frequency,the lower power consumption can be obtained.Finally,based on the characteristics of low-speed OOK signal,a low-IF image rejection receiver has been designed.This receiver uses the LC resonant network instead of the antenna to receive the signal,so the LNA can be omitted.The using of positive frequency filter with a single output,and high gain fast AGC makes the RX can get enough signal to noise ratio by using a 3bit ADC.Less amount of data can reduce the operating pressure of the digital baseband and simplify the traditional receiver structure.The three innovative structures are designed and implemented with UMC180nm CMOS process.According to the experimental result,the power consumption and chip area of 2.4GHz 1bit DSM transmitter are 5.76mW and1.5mm~2 respectively.In the 16QAM 2.5Msps modulation mode,EVM of 8.56%and out-of-band noise suppression rate of 16dB can be obtained.For 432MHz edge-combing transmitter with the output power of-15dBm,in the 50Mbps16QAM modulation mode,the power consumption is 0.47mW,and energy efficiency is 9.4pJ/bit.The chip area of this ECPA transmitter is 0.27mm~2.To the 64kbps OOK low-IF receiver,the chip area is 2.16mm~2,and power consumption is 6.8mW.This receiver can achieve 60dB dynamic range,and get54dB image rejection rate.The above three tasks have achieved the design goals of high emission rate,very low power consumption and cost-effective.