Investigation On Miniaturization Of RF Front End For Channel Emulator

The commercial construction of 4G network has been basically completed,and the research and development of 5G network is under way.The rapid development of wireless communication technique is inseparabespecially the high-performance instrument.This thesis gives a study on the le from the support of devices,miniaturization of the RF front end for channel emulator including RF transceiver flashboard and frequency synthesizer flashboard by utilizing different configuration options.In this thesis,a digital intermediate frequency system that is suitable for miniaturization is adopted.The rationality of the system scheme is verified by the link budget simulation of RF transceiver and the simulation of PLL of is carried out.Finally,the RF transceiver flashboard and frequency synthesizer flashboard are realized and the size of each flashboard is 320mm × 130mm.The thesis is composed of the following work:1)Adopting the digital intermediate frequency scheme to realize the design and implementation of RF transceiver,whose frequency is 400MHz-6GHz.The dynamic range of signals received by the RF receiver is-50dBm-+l 5dBm,and that transmitted by the RF transmitter is-100dBm?10dBm.The analog bandwidth of channel simulator could reach up to 60MHz,and the RF transceiver has a good error vector magnitude(EVM)in the whole frequency band.When channel emlator has input LTE signals of 20MHz bandwidth,the EVM of the transmitter is less than 0.7%rms and the EVM of the receiver is less than 3%rms.The EVM of receiver is 0.54%rms and the EVM of transmitter is 0.63%rms when the channel emulator works at 4.8GHz.The EVM of receiver is 0.88%rms and the EVM of transmitter is 0.73%rms when the channel emulator works at 400MHz.The EVM of receiver is 0.52%rms and the EVM of transmitter is 0.72%rms when the channel emulator works at 6.0GHz2)According to the requirements of RF transceiver system,a module that can provide frequency sources of 1.13856GHz,2GHz and 2.8GHz?6.0GHz is designed and implemented.The frequency source module adopts the structure of two-stage phase-locked loop(PLL).The first stage PLL uses the structure of integer-N PLL to realize the frequency synthesis from 10MHz to 100MHz,and 1O0MHz serves as the reference signal of the second stage PLL.The second stage PLL includes the 2GHz integer-N PLL,the fractional-N PLL of 1.13856GHz and 2.8GHz?6.0GHz respectively.The test results show that the phase noise performance of the PLL module is better than that of-93.73dBc/Hz@10kHz from 2.8GHz to 6.0GHz,and the spurious is better than-70dBc.The frequency resolution is 10Hz.The phase noise is-112.41dBc/Hz@10kHz when the output frequency is 1.13856GHz and the phase noise is-109.98dBc/Hz@10kHz when the output frequency is 2GHz.