Hardware Acceleration Design And Research Based On FPGA And Deep Learning Algorithm

The concept of artificial intelligence began in 1956.However,until the last two or three years,the application of artificial intelligence developed explosively.The reason is mainly due to the development of massive data storage and application technology.What's more,it is widely to be used that ability of GPUs with high parallel computing capabilities.The most basic idea of machine learning,as a method of implementing artificial intelligence,is to parse the data through the algorithm,sum up certain rules,and then make corresponding decisions and predictions based on the above rules.Machine learning requires a large amount of data to be trained,and various strategies are used to obtain future information prediction strategies from the data.Deeply,Deep learning is a part of a broader family of machine learning based on artificial neural network.In other words,it has many layers in a neural network.Deep learning enables machine learning to implement many complex applications,broadening the concept of artificial intelligence.Speech recognition,image recognition,machine translation,data analysis,natural language processing,smart shopping recommendation,medical prediction,driverlessness,and other functions can all be achieved through deep learning,and have achieved considerable results.Although GPUs with increasingly powerful parallel computing capabilities can handle massive amounts of data in multi-layered neural networks,they are constrained by factors such as the lack of a hardware structure for deep-learning network topologies,as well as the cycle time and high cost of developing specialized chips.The study threshold for deep learning is still high.How to implement the hardware structure of deep learning algorithm with high performance,pertinence,and short cycle has gradually emerged in the research field of deep learning.In the field of hardware acceleration,field programmable gate array FPGAs are often used for hardware accelerated development because of their high performance,parallelism,and programmable features.This article proposes to use FPGA design deep learning hardware acceleration function,mainly for the acceleration task of convolutional neural network learning algorithm,the main work are:1)Introduce the concept of artificial neural network and deep learning,and analyze the topological structure of deep learning network.Here,take the convolutional neural network as an example to explain.2)Analysis of deep learning Using convolutional neural network learning algorithms,highlighting the analysis of convolutional neural networks by adding a deep compression algorithm to the compression network,and then analyzing and summarizing the algorithm characteristics of the training process and the prediction process,in order to design the FPGA hardware computing unit.3)According to the characteristics of the training process and the prediction process algorithm,use xilinx's advanced integrated development environment Vivado HLS to design and write related code.Including the forward calculation module and the reverse calculation module,the operation unit parameters can be configured and applied to parallel computing pipeline design to meet the high throughput rate of neural networks of different sizes and reach the optimal level.4)Analyze the FPGA accelerator's data path and control path,ie the AXI communication control protocol,and write related control programs so that the easy-to-use calling program uses the FPGA accelerator for acceleration.5)Accelerometer performance is analyzed through experimental tests.The performance,power,energy consumption,and resource usage of the CPU and FPGA are tested separately,and the advantages and disadvantages of the FPGA implementation are analyzed.With the increasing demand for mobile devices and the widespread demand for artificial intelligence functions,reducing the amount of computation in the deep learning process is an innovative breakthrough.Therefore,using deep compression algorithms and implementing convolutional neural networks on FPGAs,it can be concluded that there are significant improvements in speed,power consumption,and computational complexity.