Face Recognition Algorithm And Circuit Design Based On Embedding Feature Of Convolutional Network

Face recognition is a hot topic in the field of computer vision.It has high value in security,criminal investigation and intelligent payment.With the development of neural network technology,the accuracy of face recognition algorithm has been greatly improved,and the application scenarios have been continuously expanded,which greatly facilitates people's lives.At present,face recognition algorithms carried on mobile terminals rely on GPU,which is expensive and difficult to be widely used.Therefore,the circuit design of face recognition algorithm has important practical significance and broad prospects for development.In this thesis,the author designed and optimized the face recognition algorithm and its circuit based on hardware and software co-design,and verify it with FPGA.In terms of algorithm,Tiny-densenet network is designed to improve the efficiency of image feature utilization;Lsoftmax and triplelet loss function are improved to improve the accuracy of the algorithm without additional computation;moreover,a method of parameter extraction,fusion and fixed-point floating-point for hardware implementation is proposed.In the circuit aspect,a reusable convolution acceleration array and corresponding external circuits are designed.SMIC 40nm low voltage process library is used to synthesize the DC platform,and the attributes of power consumption and maximum frequency are optimized.The logical resources are fully utilized to improve the operational efficiency of the neural network.The verification platform of the FPGA uses Miz-702N board.On the basis of convolution operation acceleration circuit,the control code is written to realize the forward propagation flow and identity judgment of face recognition algorithm.The experimental results show that the proposed algorithm achieves 93.7%accuracy on LFW open data sets and good results in natural scenes;the power consumption of convolution acceleration circuit is71.28mW,the area is 1.006mm~2,the maximum operating frequency is 200MHz,and the throughput reaches25.6 GOPS;the recognition speed of color face images with resolution of 160*160 can reach 5.5FPS on the platform of FPGA verification.This thesis has a certain reference value for future algorithm design of AI chip and IC implementation of deep neural network.