Design Of General-purpose Deep Convolutional Neural Network Accelerator Based On FPGA

The vigorous development of artificial intelligence technology not only benefits from the algorithm innovation of deep convolutional neural networks and the supply of big data,but also is driven by the continuous improvement of hardware computing performance.Among them,FPGA-based hardware accelerator design,with its advantages of high performance,low power consumption,and reconfigurability,has attracted widespread attention from academia and industry in recent years.How to make full use of the programmable resources of FPGA to design an efficient accelerator has become a research hotspot at present.This thesis chooses FPGA-based general-purpose deep convolutional network accelerator design as the research direction.First,this thesis studies the key technologies of designing general-purpose deep convolutional neural network accelerator,including: data quantization,convolution loop optimization,operator fusion and other technologies.This technical research provides a theoretical basis for the design of the network accelerator in this thesis.On this basis,this thesis proposes an FPGA-based general-purpose convolutional accelerator architecture for deep convolutional neural network.The accelerator supports the basic operator operations,and the data type adopts 8-bit fixed-point numbers,which saves computing resources as much as possible while ensuring the calculation accuracy.At the same time,this thesis deeply researches the characteristics of FPGA configurable resources,explores and realizes the optimization design of the accelerator on FPGA,improves the computing performance of the accelerator and significantly reduces power consumption.Further,this thesis builds an accelerator software and hardware platform based on Vivado.The hardware platform is based on the AXI4 bus.Microblaze processor IP is selected as the control core to interact with the accelerator and the PCIe is selected to communicate with the host computer.The software platform finishes the programming of accelerator,control processor and host computer.At last,by completing the forward inference of ResNet-50 network,the accelerator designed in this thesis is compared with general-purpose CPU and GPU.The test results show that compared with the CPU and GPU platforms,the performance-to-power ratio of the accelerator platform is increased by 307.6 and 12.9 times respectively,which has obvious advantages.Besides,comparing the accelerator in this thesis with other two FPGAbased accelerator schemes,the test results show that the accelerator proposed in this thesis can improve computing performance by up to 3.2 times,and the performance-to-power ratio by 50%.