Design And Research Of Convolutional Capsule Network Accelerator Based On FPGA

In recent years,deep learning theories and models represented by convolutional neural networks(CNN)have made continuous breakthroughs and are widely used in the field of image recognition.Since traditional CNN requires a large amount of training data and has two defects that the poor recognition of the spatial relationship between objects and the low recognition ability after a large rotation of the object,the capsule network and its dynamic routing algorithm are proposed to solve the problem.Although the capsule network is powerful and has high recognition accuracy,the model is generally used for the recognition of small-scale and low-resolution images and has poor adaptability to large-scale and high-resolution image datasets.On the other hand,in recent years,academia has proposed many neural network hardware accelerators based on FPGA platform,but there are few related researches on capsule network hardware accelerators.The model itself has a large number of parameters,and the algorithm is more complex than traditional CNN.So it is necessary to improve the performance of the model by designing its hardware acceleration circuit in practical application scenarios.In response to the above problems,this thesis focuses on the capsule network model,the dynamic routing algorithm in the capsule,and the FPGA hardware accelerator of the capsule layer.The main contents are as follows:1.First,an improved capsule network model is proposed.The convolution layer structure and activation function form for preprocessing the input image are redesigned.The dynamic routing algorithm is improved to better adapt to hardware deployment,and it is used for the classification task of large-scale and high-resolution vehicle images in monitoring scenarios.At the software level,the model can achieve an accuracy of 97.58%by using GPU training and verification,which is 2.08% higher than the original model accuracy,and the algorithm execution speed is improved about 4.62%.2.Then,based on the FPGA platform,this thesis designs the hardware acceleration circuit of the above-mentioned improved model capsule layer.The accelerator designs a data rearrangement packaging processing module to realize the function of generating the original capsule vector from the primary capsule layer,and also includes a specific systolic array and multiply-add array which are used to process the vector and matrix operations of the internal algorithm of the capsule layer with the corresponding hardware activation unit and data buffer.The overall controller is designed using the idea of finite state machine and pipeline to schedule the execution process of the algorithm on the FPGA.3.Finally,this thesis selects Altera's FPGA device and its corresponding EDA tool to synthesize and implement the overall circuit of the accelerator,and quantifies the trained weight data and stores it in the on-chip storage space of the FPGA,and conducts the overall system simulation verification.The experimental results show that the recognition accuracy of the FPGA accelerator can reach 92.75%.The peak computing power is about 1.38157 TOPS,and the energy efficiency ratio is about 0.16198TOPS/W.Compared with the forward inference of the model executed on the GPU,the time consumption on the FPGA is reduced by about 23.86%,and the power consumption is reduced by about 96.12%.Compared with the hardware acceleration schemes provided by other literatures,the accelerator designed in this thesis also achieves a better acceleration effect.