Design Of Millimeter-Wave Broadband Tripler On CMOS Technology

As an important unit for the front-end,the frequency multiplier has great impact on the performance of high-frequency electronic systems.With the application and development of millimeter wave technology,it is urgent to research the frequency multiplier as the signal source of high stability and good phase characteristics.Therefore,this thesis is based on the 65-nm CMOS process and has completed the design of a tripler monolithic microwave integrated circuit(MMIC)in Ka(26.5 ~ 40GHz)band.First of all,this thesis makes a brief survey of the research status of the millimeter-wave multiplier and power amplifier both domestic and foreign in recent years,and summarizes the technical specifications,the common topology and development situation,after these,introducing the basic theory and working principle of the frequency multiplier and power amplifier.Secondly,in the circuit structure,this thesis adopts a front tripler and a post-power amplifier to form a ka-band tripler with high output power.Among them,the front tripler uses transformer to form differential configuration and make impedance conversion of the input and output side.The bias of the MOSFET is selected to make it work on the class C for rich harmonic three times.The simulation results show that the maximum power gain at the 33 GHz frequency is-6 d B and the harmonic rejection is more than 7 d B with 10 d Bm input power.3-d B bandwidth is 33 GHz(24 ~ 57 GHz),the maximum output power is 0 d Bm,the layout size is 792×560 um2.The post-set power amplifier is a 3-stage common source structure circuit based on the testing of a 2-stage common source structure PA after tape-out for increasing the power gain.The PA of two types uses the multi-branch matching method and the filter effect of the bias circuit for broadband matching network.Patterned ground shield under the RF signal line is used to reduce the loss and area for both types of the PA.The results of the measurement show that the 2-stage PA obtains a maximum small signal gain of 7 d B from 24 to 52 GHz.The measured saturation output power(Psat)is 14.1 d Bm at 35 GHz with 12 d Bm of output 1 d B compression point(P1d B)and the power added efficiency(PAE)is 9.6% at 40 GHz,under 1.2 V supply voltage.The chip size without pad is 434 × 184 um2.Finally,it is the integration design and simulation of MMIC for the pre-tripler and post-power amplifier.Through the overall simulation,the maximum power gain of the tripler with input power of 10 d Bm is 7 d B,and the 3-d B bandwidth is 21 GHz(28.5 ~ 49.5 GHz).At the 33 GHz,the maximum saturation output power is 13.2 d Bm,1d B compression point output power is 12 d Bm with 7.5% additional power efficiency and 169.56 m W DC power consumption,the harmonic rejection is more than 8 d B,the layout size is 1421×592 um2.In this thesis,the design and simulation methods of Ka-band tripler and power amplifier are analyzed and summarized in detail.Based on 65 nm CMOS process,a tripler millimeter-wave MMIC is designed.It provides reference for the design of millimeter wave tripler.