Research And Design Of SOC System Clock Circuit PLL IP Core

The rapid development of integrated circuits has improveed people's lives constantly,and the growing social demands drive integrated circuits towards system on chip(SOC).The SOC includes many functional modules:microprocessor,memory,analog IP,digital IP etc.In order to achieve the complex system functions.these modules need to work under certain timing conditions.Therefore,it is necessary to design a clock signal source circuit that can satisfy each functional module.The clock technology based on phase-locked loop(PLL)has the characteristics of simple structure,good jitter performance,wide frequency range and easy realization.It has been widely used and developed,and it has also become one of the main choices of clock generator in the system integrated circuit.In the SOC,it is hoped that the functional modules will be IP-based.Therefore,it is of great significance and value to research the clock circuit PLL IP cores that are used in the SOC system.Firstly,this essay has completed the theoretical research of the SOC and PLL system,and has analyzed the basic framework of a typical PLL system.The key performance indexes of PLL system are given.Then the basic model of PLL system is analyzed and researched.And the key circuit module of charge pump phase locked loop(CPPLL)is studied and analyzed in detail,especially the analog circuit modules such as voltage controlled oscillator,charge pump,loop filter and so on.The advantages and disadvantages of the different circuit structures are compared and analyzed,and the improvement method is put forward.This part of the work provides the theoretical basis for the selection of the circuit structure for the subsequent design of the PLL clock IP core.Next the whole design of the PLL clock IP core is completed,which includes the design and simulation of the key circuit modules.In particular,a novel low voltage and low power Pseudo differential ring voltage controlled oscillator is designed.The voltage controlled oscillator conducts the inverter including a rail current source as a basic delay unit,and the linearization technology is used to improve the linearity.The circuit has the characteristics of simple structure,easy realization,low voltage,low power consumption and low phase noise.Then the matlab and cadence spectre are used to verify the design of the PLL clock IP core,including its linear characteristics modeling analysis,simulation verification,the overall transient output verification,system performance indicators verification:settling time,output jitter etc.Finally,the layout,post-simulation and function testing are implemented.The PLL clock IP core finally realized in this paper has an input clock frequency range of 10-60 MHz,an output clock frequency range of 10-600 MHz,lock time less than 40?s,P-P jitter less than 10ps.The power consumption of the chip is 12mW when the reference clock is 25MHz and the output clock is 600MHz.The PLL clock source IP core can be quickly locked at required frequency,and works steadily.It meets the design requirements and has been applied to SOC system successfully.