The Design Of Intelligent Internet Of Things Chip Based On RI5CY Processor

The Internet of Things is an important part of the information technology of the new generation.It is also an important development product in the age of "informatization",and it is also the important industrial revolution that changes the human life form after the Internet.At present,various kinds of Internet of Things based on cloud platform include intelligent community,intelligent medicine,intelligent home and so on,which have been established gradually,greatly facilitates the human production and living.However,as a large number of intelligent material devices are connected to the network,the amount of network data will explode,which will paralyze the network,slow the reaction of endpoint devices,and even have a hidden danger.In order to overcome the influence of mass data,it has far-reaching strategic significance and application value to design a core chip of intelligent object with intelligent device perception ability and data processing ability.In this thesis,an intelligent chip design scheme for the Internet of Things with intelligent recognition is proposed by using the method of IP core reu se.The chip uses AMBA 4.0 AXI bus to carry RI5 CY open source processor,AHB high-speed subsystem and APB low-speed subsystem,high-performance intelligent modules such as CameraIP,MemCtrl,ANN are mounted on the AHB high-speed subsystem,while the APB low-speed subsystem is mounted with UART,IIC,GPIO and PWM.Based on the inherent parallelism of artificial neural network structure,this thesis accomplishes the design of ANN hardware acceleration module.Among them,the processing elements chain module adopts the systolic array to solve the data blocking problem in the ANN operation process in a pipeline manner,and the dynamic adjustment and rational use of PE unit can be achieved according to the network size,that is,for small networks with less PE units to complete network operations at lower power consumption,8 PE units can be used to run parallel neuron operation in large networks,and 64.25 times faster than other Ann serial implementations.Finally,a complete system verification platform is built for the whole intelligent chip system.Modelsim function simulation and FPGA prototype verification are carried out,in the system,the application test of real-time recognition camera image based on ANN Hardware acceleration module is completed.The intelligent Internet of Things chip designed in this thesis first carried AI module,which can realize real-time recognition of handwritten characters at the terminal of intelligent equipment,effectively reduce the transmission of edge data.Simultaneously,the overall performance and power consumption of the system chip are evaluated.The results show that the function,performance and power consumption of the intelligent chip system of the Internet of Things are in accordance with the design requirements.