| In recent years,with the improvement of living standard,people have put forward higher requirements for the performance of mobile electronic equipment.As the core unit of the chip,CPU(Central Processing Unit)becomes more and more important.However,on the one hand,the MOS transistor has reached the physical limit,on the other hand,on the other hand,CPU manufacturers such as ARM are charging higher and higher patent fees,the development of CPU has entered a bottleneck period.RISC-V(Reduced Instruction Set Computer Fifth Edition)is a kind of instruction system introduced by D.patterson team in 2014.It has the characteristics of short,concise,easy to expand,easy to implement and fully open.Therefore,with the rapid development of artificial intelligence industry,people began to search for the architecture of CPU+neural network accelerator to improve the computing power of the processor.However,because of each version of ASIC needs to be customized according to the needs while realizing neural network,the design leads to high cost.In addition,after FPGA is burned and writen,the whole circuit is determined,which makes FPGA lack of flexibility and high price.Therefore,the best choice is to use RISC-V kernel and the co-processing accelerator architecture which can realize neural network instruction.This paper is devoted to the design of a neural network accelerator based on RISC-V.This paper first introduces the architecture of RISC-V,the principle and method of instruction extension.Then,based on the core of hummingbird e203,the accelerator with convolutional neural network function is extended,which accelerates the operation of instructions.Among them,the accelerator changed the traditional CPU data movement form,used pulse array,data reuse and other methods,improved the data parallelism,reduced the data flow between the processing unit and memory repeatedly.In order to realize data reuse,this paper also uses the weight reuse method to reduce the access of accelerator to memory.Finally,each module of the accelerator and the whole system are simulated and verified on the vivado platform,and the hardware resources used in the system are analyzed.The results show that the architecture using accelerator is 4.1 times faster than the architecture without accelerator.For active and pooled computing,the architecture using accelerator is 1.3 times faster than the architecture without accelerator.At the same time,the resource consumption table shows that accelerator accounts for about 40% of the whole system.The power consumption table also shows that the dynamic power consumption of the system accounts for65%,which is 0.142 W.MMCM(mixed mode clock manager)and Bram(block random access memory)occupy most of the power consumption,which are 0.119 W and 0.011 W respectively,while the static power consumption uses the remaining 35%,which is 0.076 w. |
