The Design Of RISC-V Processor Suitable For Accelerated Convolutional Neural Network On The Edge Side Of The Internet Of Things

In recent years,convolutional neural networks(CNN)have achieved great success in engineering applications such as image classification and face recognition in devices on the edge side of the Internet of Things(Io T),and have been widely used.Nowadays,as the topology of the CNN model continues to deepen and rapid growth of the number of Io T devices,more and more CNN computing tasks need to sink to the edge-side devices to perform.However,the processor of the traditional edge-side device uses a general-purpose computing architecture,which is only suitable for control tasks and lightweight operations.When faced with computationally intensive tasks such as CNN,there are problems such as poor real-time performance and low energy efficiency.Therefore,it is necessary to design a processor with both high computing performance and low energy consumption to meet the needs of the edge-side devices of the Internet of Things to perform CNN algorithm tasks.This paper focuses on engineering issues such as poor real-time performance and low computational efficiency when the CNN algorithm is executed on the edge-side devices of the Io T,and designs and implements a RISC-V processor with an on-chip extended Winograd fast convolution algorithm circuit architecture.To meet the needs of low-power,small-area engineering applications on the edge of the Io T,a RISC-V processor with a 2-stage pipeline,single-transmission,out-of-order execution,order write-back architecture,and Harvard storage architecture was designed.Introduce BTFN static branch prediction mechanism,combined with bypass and blocking strategies,separately deals with pipeline control hazard and data hazard to achieve a compromise between performance,area,and power consumption.At the same time,this paper combines the scalable features of RISC-V to design and integrate a new type of convolutional neural network hardware acceleration circuit based on the Winograd algorithm in the manner of extended instruction set,which reduces the complexity of the traditional algorithm on the basis of considering the flexibility of software,and improves the computing performance and energy efficiency of the processor performing CNN tasks.In this paper,a RISC-V processor with extended Winograd convolution acceleration instruction set is designed based on Verilog HDL,and the functional simulation of the processor is completed using Vivado 2019.1.The processor prototype verification is completed based on Xilinx Artix-7 FPGA platform and HH 0.13?m CMOS process was used to complete the ASIC implementation.Finally,under the same process platform and constraints,the design of this paper and open source RISC-V processor"Hummingbird E203"are compared in terms of area resources,program performance and other indicators:the results of the software and hardware collaborative verification of the 3D convolution program are shown that the area cost of the ASIC designed in this paper increases from 264591.08306?m~2to 294006.9023?m~2,which is 111.12%of the comparison object;the amount of assembler is reduced from 1824 to 120,which is 6.6%of the comparison object;the program running time is reduced from 242.8?s to 41.1?s,which is 16.93%of the comparison object;the energy consumption is reduced from 37.634?W to 6.5349?W,which is 17.36%of the comparison object.The data shows that the design of this paper realizes a processor with both high computing power and low energy consumption to meet the needs of the CNN algorithm task performed by the edge-side devices of the Internet of Things while increasing the area overhead.