Font Size: a A A

Research On The Development Platform Of Artificial Intelligence Chip Based On RISC-V And NVDLA

Posted on:2021-02-20Degree:MasterType:Thesis
Country:ChinaCandidate:Z Y ZhouFull Text:PDF
GTID:2428330605950773Subject:Electronics and Communications Engineering
Abstract/Summary:PDF Full Text Request
As Moore's Law comes to an end,it will become more and more difficult to blindly compare hardware performance by improving the process.How to improve the hardware architecture to adapt to the ever-changing artificial intelligence algorithms becomes increasingly important under the current situation.This paper builds an artificial intelligence chip research platform based on open source hardware framework in order to study the design of the software interface from the bottom hardware to the upper layer and to ensure that the design of the bottom and upper software interfaces of the chip meets the needs of specific applications.This article first briefly classifies the current artificial intelligence computing platform,introduces the RISC-V instruction set and three open source processor cores based on the RISC-V instruction set,analyzes the hardware acceleration framework NVDLA and makes simple instructions for its system and the internal module functions.Based on this,the main design work is introduced:(1)According to the RISC-V instruction set expandable instruction method,I design a SIGMOD activation function instruction by using reserved instruction encoding space.then define the six states of the operation module including the external interface of the system as a whole,and finally simulate the specific operation circuit.(2)According to the NVDLA CNN acceleration framework,I design hardware accelerators from two aspects of computing power and bandwidth.Convolutional neural networks mainly use two operations: convolution and pooling.The hardware design of these two kinds of operation paths is made respectively,then the circuit functions are simulated,the respective driving functions are encapsulated,and the function configuration parameters are explained.A memory access module is designed to accelerate data transmission and improve bus access efficiency in order to reduce the limitation of the bandwidth on the hardware accelerator.(3)A ZYNQ FPGA prototype board and supporting PYNQ software are used to build a software and hardware verification platform,which verify the function of the RISC-V custom activation function instruction and the hardware acceleration driver.I build a small convolutional neural network based on the mnist data set,implementthe entire network configuration and inference on the pynq-z2 hardware platform.The handwritten digits are recognized correctly finally.
Keywords/Search Tags:artificial intelligence, open source hardware, custom instructions, hardware acceleration
PDF Full Text Request
Related items