Design Of ADC Used In DRM/DAB System

With the continuous development of mobile communication technology,the requirements of communication systems for the analog-to-digital converter continue to increase.Low-power analog-to-digital converters with certain precision become one of the popular direction.In this context,successive approximation analog-to-digital converters(SAR ADC)have developed rapidly in recent years due to their low power consumption and easy algorithm advantages.In this Thesis,the research status of successive approximation analog-to-digital converters is studied,and the basic parameters of analog-to-digital converters are introduced.The realization principle of various common types of analog-to-digital converters is described.According to the requirements of DRM/DAB system,the structure and design index of successive approximation analog-to-digital converter are determined,and the design of low power successive approximation analog-to-digital converter is completed.In this Thesis,the working principle of capacitive DAC in successive approximation analog-to-digital converters is analyzed in detail.The capacitance array structure of 5-5 segment and the capacitance value of high to low bits are determined,and the reference capacitance area and analog-to-digital converter The relationship between the DNL and derived the reference capacitance is 50fF.Use the center-symmetric layout to optimize the performance of the capacitor.The key indicators of the comparator in the analog-to-digital converter are analyzed:offset,gain and response time.The multi-stage comparator and dynamic latch cascade are used to realize the high-speed and low-power comparator,which reduces the dynamic comparison The effect of the feedback noise on the DAC.And the use of the output offset cancellation technique reduces the overall offset of the comparator.The non-ideal factors of the sampling switch are analyzed in detail by using a bootstrap switch,which does not overlap the clock and fully differential reference signals,reducing non-ideal factors such as charge injection,clock feedthrough,and non-zero on-resistance of the switch Impact.The timing logic of the whole circuit is designed,and the digital module is verified by Verilog code,and the digital module is generated by DC and Astro.This paper based on SMIC 0.18?m CMOS technology to complete the circuit design and layout optimization.In the case of power supply voltage of 1.8V,the use of 4.76563MHz,1.6V sine wave input after the simulation,the equivalent number of bits is 9.2 bits,the signal to noise ratio of about 56dB.The average current of the high-speed comparator is only 432.2pA.