Design Of 3-GHz CMOS Multigain LNA For Wireless Communication

Demand has grown for wireless connectivity for applications in the area of wireless sensors networks,IoTs,and RFID.This growing demand has called for SOC design to focus on lower costs,lower power consumption,and more miniaturised solutions.Due to their unique low cost and significant integration advantages,CMOS technologies have become dominant for designed transceivers.Since LNA is the first building block of the receiver's end,it decides the sensitivity of transceivers.It is therefore both critical and challenging for LNA design to meet different application standards like ZigBee,IEEE802.11xx,BLE&RFID.This thesis focuses on the integration of different wireless standards such as the multigain,low noise considerations,differential structure,high linearity in terms of IIP3,and low power consumption to design a CMOS low noise amplifier for the frequency band of 3.00-3.04(GHz).The LNA is implemented using CMOS GF-130nm process technology.The LNA consists of input matching,a multigain core amplifier,output matching,and differential structure.The LNA's sensitivity and power consumption at high frequencies typically depend upon the tight input matching criteria.This is because a LNA varies from a weak input RF signal to a higher signal and consumes more power.This thesis addresses this problem using multigain cascode technique to implement different gain modes without influencing the input and output matching mechanism.This thesis propose to implement the inductive source degeneration with a high Q-factor centre-tapped inductor for low noise consideration.Additionally,tight matching will be implemented,which limits the noise figure to<4 dB.Post simulations illustrate how the LNA exhibits the minimum noise figure of 3.81 dB through the application of a multi-step optimization technique.For multigain core amplifier modes at the 3-GHz centre band,this thesis proposes a multigain cascode technique.This technique can be implemented by using the different gate bias control signals of VHigh,VLow,VMid,and VSleep to operate the transistors in the sub-threshold region.This has the effect of reducing the main gain per cascode stage by 3-5 dB.The LNA exhibits four gain modes:23.2/19.1/15.1/11.1 dB as demonstrated in post simulations.At high frequencies of>2-GHz,the output of a LNA is directly coupled to the mixer.Due to parasitics,a LNA could provide a phase shift of few MHz and may lead to a change in the performance metrics in terms of gain reduction,common mode noise,and low IIP3.To address this issue,differential structure,tight output matching,or a multi-tap inductor based solution is required.For tight output matching and differential structure problems,this thesis propose to implement LC-based matching with a high Q-factor centre-tapped inductor for differential and multigain modes without having an effect on output matching.The reference voltage of 0.6 V is used to operate the input core amplifier to work in the sub-threshold region.The gate bias control voltage of 1.5 V is used for multigain cascode structure to work in the subsequent region.The power consumption is around 3.6 mW per mode and 2-mA current,which is according to gain and noise figure trade-off.The linearity factor IIP3 ranging from-6.52 to-0.96 dBm for different modes.The LNA covers the area of 0.63mm2is on the whole receiver chip.For post-simulations,the test bench is implemented by the off-chip input matching structure.Input RF matching is performed by the off-chip gate inductors on the PCB using Cadence Virtuoso ADE.For the simulations,an equivalent wire bonding inductance of 1-nH is added with an ideal balun.The subsequent S-parameters are used on Cadence Virtuoso ADE for gate inductors with n-port to obtain the real-time response.