Cascade Coding In Satellite Communications And Fpga Implementation

This thesis mainly focuses on the encoding and decoding strategy and their FPGA-oriented realization for a certain portable satellite communication terminal. The resulting error control codes (ECC) module with FPGA is applied in the portable satellite communication terminal.At first, the system scheme of the terminal is introduced. Secondly the principles and the algebraic configuration of the ECC for Reed-Solomon code, interleaving and convolutional code are discussed. According to the algebraic configuration, the ECC with FPGA and VHDL on the platform of QuartusII is realized. Then, a test module to verify the results of the Quartus's simulation with Matlab languages is built. In the end, the bit error rate (BER) performance of the terminal is listed.The BER performance shows that the proposed ECC module meets the requirements of the project.