CPFSK Modem Design And Implementation

The thesis studies the implementation of CPFSK modulation and demodulation communication system. It mainly includes m sequence encryption and decryption circuit, RS encoding and decoding circuit, interleave and de-interleave circuit, convolutional encoding and decoding circuit, CPFSK modulation and demodulation circuit.Implementation of each constituent module is discussed followed by an overall workflow of the system. Verilog is used to design and implement32m sequences encryption and decryption circuit based on the FPGA in the encrypted part. The system uses a method of cascaded RS(255,239) code and (2,1,7) convolutional code to realize error correction, and inserts a interleaver in the two encoders to improve the performance of error dectection. For RS (255,239) encoding circuit, this thesis improves the traditional coding algorithm and implements the algorithm on FPGA by utilizing Verilog. Altera IP core is taken into account to implement RS (255,239) decoding circuit. We also study the rate matching and deserializing, and propose solutions to the problems in RS encoding and decoding circuit. This thesis implements the convolutional interleave and de-interleave circuit and (2,1,7) convolutional encoding circuit on the FPGA platform and Altera IP core is also used for implementation of (2,1,7) convolutional decoding circuit. As a special form of CPFSK, MSK is used in modulation and demodulation system. We implement the classic quadrature modulation circuit of MSK by Verilog. And we also design and implement a simpler and more efficient MSK demodulation scheme based on DFT algorithm by Verilog. Furthermore, the thesis makes simulation of each module on Matlab to ensure the correctness of circuit design.