Research Of T-AES Encryption Based On FPGA In 10G EPON

The core task to achieve the "tri-networks integration" is to promote the construction of Monet.With the steady progress in the construction of Monet,10G EPON as an important and mature technology of passive optical networks for that 10G EPON has prominent ad vantages such as lower cost,flexible functions of business,upgrade easily,etc.,10G EPON is considered to be one of the resolutions in city optical network construction of "tri-networks integration".10G EPON gets a lots attention because of the potential security problems leaded by its simple topological structure while 10G EPON is adopted widely by governments and companies.At the same time,the network usage and frequency are becoming more and more high in these recent years,so how to ensure the privacy of users and security of network will become the focus in future.To let 10G EPON network has more extensive application in the future when "tri-networks integration" realized completely.This article gives the full analysis of 10G EPON system structure and related detailed principle,and also aiming security threats exist come up the resolution which could protect the users' private and the security of system.The paper is based on the 128 bit AES algorithm,introduce a timestamp extracted from 10G EPON system ranging and add it into the AES algorithm key expansion,achieve the effect that the round key can change over time dynamically update.The article also realizes this resolution in FPGA,by designing the schematic diagram and function module according to Top-Down,and writing and debugging with hardware language Verilog HDL.In the process of FPGA design of T-AES,the system is divided into logical functions,improving the efficiency according to the assembly line.At last,simulate the FPGA module of scheme with timing sequence,the simulation content contains simulation of encryption/decryption and simulation of cipher text change with timestamp,the detail simulation result is given out and the result prove that the FPGA design of T-AES in 10G EPON is accord with the requirement of original design.