.802.3 Fast Ethernet Mac Layer And Its Fpga Implementation

The implementation of IEEE802.3x MAC(Media Access Control ) function isdesigned based on Altera's FPGA in this dissertation. VerilogHDL is used for thisproject. The IP core's synthesis, place route and assemble was based on developtool QuartusII4.0. The timing simulation was based on Modelsim . At last, designmodule is downloaded in develop kit upon which real-time simulation was done toanalyse the waveform with Agilent's Analyzer 1673G .The protocol of Ethernet and theories about the PON(Passive Optical Network)over Ehternet is introduced firstly.Then the master plan, including the architectureof the system, the module dividing, the design method and the coding style isexpatiated. After that, the detail of each module with testing data results and thetiming simulation waveform is given out,.Solutions to the key functional modules of MAC layer are given based onFPGA and HDL in this dissertation, such as Rx module, Tx module, MAC-controland interface between PHY,MAC and host, arithmetic for CRC,CSMA/CD andHASH Table , model of cycle request argorithm as well.While designing the system, it is very important that how to divide and defineeach module and how to coordinate and interconnect these modules. Method ofTop-down are also apply to design.As for the interconnection of each module, theinterface signal is defined to communicate between them, and the internal timing ofthe module is control1ed by states machine. When constructing the code, it shouldbe attention to hardware resource spending and concurrent executable ability of theVerilog Language to make the design close to the hardware working way, so itcould match a high speed with a low hardware spending to satisfy the demand ofthe cost, performance and practicability.Finally the theory of the MPCP(Multiplex Point Control Protocol ) in EPON'sis also reaserched. It give mathematics deduce and example for DBA(DynamicBandwidth Allocation) , dicusse the method to realize adding it to 802.3 MAClayer.