FPGA-based Ethernet Packet Timestamp Marker Unit Design

The implementation of IEC 61850's timestamp marker unit is designed based on Actel's FPGA in this thesis. Development of substation automation, timestamp marker unit in the role of automation in the substation, development of Ethernet and IEC 61850 protocol are introduced first. Then, the main system introduction is provided, including the internal architecture of the system, the module category, the design method and also the coding style is expatiated. After that, the environment of development,the verification tools, the detail of each module with testing data results and the simulation waveform in time domain are given.Solutions to the key functional modules of timestamp marker unit are given based on FPGA and HDL in this thesis, such as TX module, Time module, CRC module, CRC encoder module and PHY configuration module as well.Verilog HDL is used for this development. The IP core's synthesis, place route and assemble are based on the develop tool Libero IED v9.0. The timing simulation is based on Actel Modelsim6.5. Finally, soft core is downloaded onto the Actel's ProAsic A3P1000 FPGA for verification and test. Top-down method is also applied to design this system. The functional verification of this design includes functional simulation, timing simulation, board-level debugging, and system testing. In the design of the IP core, we should try to implement it by hardware and take the optimization of the internal resource in FPGA chip into consideration. The concurrent executable ability of the Verilog Language should be considered as well. With these efforts, the system design could match the requirements of high speed process with a small area, low cost of system implementation, high performance and practicability.