Research And FPGA Design Of Advanced Encryption Standard

In October 2000, National Institute of Standards and Technology(NIST) has decided to select the Rijndael algorithm as the Advanced Encryption Standard(AES), that means Rijndael algorithm will play an important role in data encryption for a long time. This thesis is concerned chiefly with the study and research of design principle, security, randomness and hardware implementation of the Rijndael algorithm.One important aspect of the cryptographic algorithms localization is to eliminate the suspicion of a trapdoor. Mathematical basis, whole architecture and all layers' features of Rijndael algorithm is dealt with in detail in order to make sure weather Rijndael algorithm has trapdoor or not.Security of Rijndael algorithm is the most important in all features, which is studied on the view of resistance against all known attacks. According to features of the S and P layers, ability which Rijndael algorithm has to resist against Differential cryptanalysis and Linear cryptanalysis is theoretically discussed, and the principle of Square Basic attack and two kinds of extension attacks are discribed on the basis of the characteristics of oriented -byte of Rijndael algorithm. At last, an algebraic representation of Rijndael algorithm is deduced starting from that of S-box,which is used for interpolation attack.A practical Rijndael algorithm should have the great statistics feature, i.e. randomized ability of data. Several test items are built on the basis of the efficiency and diffusion of data transform, and way which is used for every test to construct its data.Rijndael algorithm which has the great implementing feature is readily to be implemented in software or hardware. This thesis mainly deals with the hardware implementation of Rijndael algorithm, finish VHDL coding of feedback mode and non-feedback mode, which is based on FPGA.