The Research Of Multiple Bits-Flipping LDPC Decoding Algorithm Based On Solid State Disk Drive

With technological innovation of storage system,the NAND Flash as the storage medium of solid-state storage system(Solid-State Drive,SSD)because of its features such as high performance,low power consumption,high speed,speaking,reading and writing,and has gradually been applied to the Internet,military,automotive,aerospace and other fields,is one of the main trends of the development of storage system today.However,with the development of Flash technology level,especially the development below 25 nm,combined with the structure of Flash from SLC to MLC even TLC,unit storage capacity of one Flash Cell has been improved for several times,the storage density of one Flash Cell is higher and higher,but the row bit error rate increases a lot within flash storage.However,existing solid-state storage system data fault-tolerant is still dependent on traditional magnetic storage system error correction technology,not completely accords with the technical characteristics of solid-state storage medium,is difficult to make full use to the SSD performance advantages.LDPC as a kind of excellent error correction performance and the error correcting code with parallel characteristics such as fast decoding,also gradually applied to the SSD.However,the high coding rate,large storage density and small hardware space in the field of solid state storage put forward more challenges for the application of LDPC in the field of storage.Therefore,in this paper,based on the random error characteristics of Flash NAND,a multi-bit flip efficient LDPC decoding algorithm is studied.The main work of this paper includes the following aspects:1.Firstly,a new algorithm of multi bit flipping decoding algorithm named WMBF is proposed.The proposed algorithm can achieve multiple potential error bit a iterative parallel flip,can improve the decoding efficiency;also by iteratively updating the weights,effectively reducing the same bit was repeatedly flipping probability,improve the decoding accuracy.Experimental simulation results show that the proposed algorithm can effectively improve the error correction performance of bit flip,especially to obtain a better decoding speed,and higher error correction capability.2.On the basis of WMBF,this paper proposes a DER-WMBF algorithm which is suitable for SLC and NAND Flash MLC,which is based on the dominating error region.The proposed algorithm is proposed according to the characteristic of Flash itself.The algorithm can effectively overcome flipping decoding algorithm for decoding process even a bit flips in the lead to the shortcomings of the decoding error and suppress the spread of false information in the decoding process,the simulation experiments show that the algorithm effectively improve the decoding error correcting capability,and the decoding speed is increased.3.Finally,this paper in view of the existing various improved BF&the WBF algorithm decoder logic circuit implementation of flip logic serial design flaws,combined with WMBF decoding algorithm characteristics of and put forward the implementation of parallel decoding flip logic module logic circuit based on WMBF,to increase a small amount of logic circuit overhead,parallel multi bit flipping function can be achieved WMBF,enhance the error correcting capability of the system.