Software And Hardware Implementation Of Signal Processing For Shipborne Fire Control Radar

As an important part of the surface warship weapon system,naval guns play an important role in low-intensity maritime conflicts and terminal anti-missile air defense missions.In modern warships,naval guns often work in conjunction with fire-control radars.The targets are detected and tracked by the radar,and the target information is transmitted to the control system.The naval guns are responsible for firing at the target.In this paper,based on a shipborne fire control radar signal processing project,the theoretical analysis and hardware and software implementation of the related single-target radar signal processing algorithm are carried out.This paper firstly introduces the signal processing algorithm of echo baseband signal under single target system,introduces the theory and principle of the main algorithm,then analyzes the characteristics and calculation of different algorithms,and plans the implementation of the algorithm to FPGA or DSP chips.Then introduces the design and production of the signal processing PCB board.Firstly,the paper analyzes the indicators proposed by the project,and determines that the main structure of the board is 1 FPGA chip plus 2 DSP chips,and then more specific calculations are performed on different algorithms.The amount is estimated to complete the chip selection.Then introduce the design of important peripheral systems such as power scheme,clock scheme,data interface and storage scheme in multi-band signal processing board,and briefly analyze the layout in PCB design.Then introduced the preliminary debugging work after the completion of the board production,such as power-up,power-on sequence and static power consumption,and finally we completed the design and production of the board.Finally,the FPGA implementation of pulse compression algorithm,MTD algorithm and CFAR algorithm is introduced.An improved method is proposed for the pulse compression algorithm in the frequency domain.Compared with the traditional pulse compression algorithm,the new algorithm can save 16.6% to 44.4% of BRAM resources in different points in the pipeline mode,and the operation time can be saved by about 50% under all points.New algorithm can also saves 16.7% to 39.3% of computing time in different points in serial mode.Because the new structure of the pulse compression algorithm requires a specific structure of the FFT algorithm,and the Xilinx official FFT algorithm IP core has a fixed structure immutable,and only have the radix 2 structure in the pipeline mode.To solve this problem,this paper also designed new hybrid radix 2-4 Serial FFT algorithm and pipeline FFT algorithm.A RAM read-write scheduling method based on serial FFT algorithm is proposed.The N-point FFT algorithm can be realized by using RAM with a total depth of N.In this paper,N-point serial FFTs are implemented using two N/2-depth RAMs.The algorithm has a frequency greater than 250 MHz after the synthesis and implementation.Then the implementation and test results of the MTD algorithm are introduced.The matrix transpose of the MTD algorithm is tested and analyzed,and the inadequacies and directions for improvement are summarized.Then the design and test of the CFAR algorithm are summarized,the information processing results in the DSP chip are given,and finally the debugging of the fiber interface,SRIO interface and Gigabit Ethernet are briefly introduced.