Graphical Design And Implementation Of Radar Active Jamming Based On System Generator

Field programmable gate array(FPGA)is the core component of signal processing for modern radar jammers.However,most of the algorithm researchers do not know much about the hardware programming of FPGA,which makes the hardware implementation of the algorithm less efficient and seriously restricts the rapid application of many new technologies.In order to make the programming realization of FPGA more efficient,more modular and standardized,this thesis systematically studies how to implement graphical FPGA algorithm based on System Generator catering for the rapid realization of radar jamming algorithm.The main innovative works in this thesis are as follows:1.A typical System Generator model of radar jamming signal processing algorithm has been designed.In view of the requirements of typical radar active jamming technology,a series of jamming algorithm basic modules are designed based on System Generator including DDS,FIR filter,storage replication,pulse detection,narrowband Gauss white noise,and so on after analyzing all kinds of DRFM jamming.And then by assembling these basic models,the System Generator model of DRFM jamming such as noise frequency modulation jamming,noise amplitude modulation jamming,noise phase modulation jamming,interrupted-sampling and repeater jamming,frequency shift jamming,forward pulse replication jamming,convolution noise jamming is designed.2.The feasibility and versatility of System Generator model have been verified by experiments.First of all,the above models are tested on the Xilinx Kintex Ultrascale KU115 high-performance FPGA chip.At the same time,a set of System Generator models,such as multichannel parallel DDS,orthogonal sampling,multiphase filter,digital down conversion and digital up conversion are designed.The test results show the effectiveness of the models established in this thesis.In order to verify the universality of the FPGA design method based on the System Generator model,the algorithm was transplanted with the mainstream Xilinx Virtex7 VC709 development board as the hardware platform.Practice has proved that this method is efficient and universal.The research of this thesis provides a new technical idea for the algorithm researchers to simulate and verify the radar jamming algorithm quickly.It can effectively shorten the design cycle and make the design of the algorithm more modular and standardized.It has important engineering value.