| With the development of shipping industry, the study of basic principles and engineering applications about the marin navigation radar which is used as an important device for vessels to avoid obstacle, navigation and orientation become more and more valued. In order to get longer time to use, increase range resolution and be more healthy to people, the marin radar gradually transits from the traditional magnetron-mode radar to the solid-state continuous wave and pulse-compression mode radar. But the technology of solid-state radar is more complex than magnetron-mode radar from RF circuit designing to IF signal processing. And one-time investment cost is also higher. These disadvantage directly affect the widely use of solid state radar in the civilian ship radar field. This article proposes a new design ideal about the digital signal procession of the solid-state marin radar which is based on pulse-compression. The scheme uses only one chip of FPGA to get three kind of chirp pulse signal compressed which can meet the requirements of different ranges and distance resolutions of a marin radar. These methods can be sought to obtain lower cost, better versatility and blameless function. In this way, the application of solid-state marin radar will be pushed.The time-bandwidth product of three kind of chirp signal that to be compressed are all 30. And the time widths of them are 1us, 3us and 6us. Under 120 MHz sample rate, they go through a DDC module to get two baseband signals with 60 points. The DDC module is composed of a CIC filter, a half-band filter and a fir filter. Some stage of these filters will be skipped when the extraction rate less than 12. In the matched filter design, the filter coefficients are weighted by hamming window to suppress the side lobe. And according to the characteristics of large gate count of marin radar, the structure of time domain implementation is used to realize the matched filter module. After the pulse compression the data goes through the pulse accumulation module to increase the SNR. Then the output data is processed by the CFAR module to improve the accuracy of target detection. These modules work in pipeline structure mode and are control by the center module.A signal processing board is designed to meet the requirement of the item. It composes of the FPGA and some other chip circuit. On the board the high speed AD converter can sample the signal within 200 MHz bandwidth, the net port module can realize the speed of 100 Mbps and the DDS can modulate many kinds of signal within 400 MHz. This board fits to medium scale and high real-time requirement system.The test result of the design shows that the three kinds of chirp signal are all can be compressed to get the sidelobe supression ratio to be more than 30 dB which means that multi-range can be realized, the data processing rate can reach 720 Mbps and the range resolution can reach 7.5m. The pictures that show on upper monitor are clear, short of clutter and have good real-time. These all indicate that the design is very practicable. |
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