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A Research Of Fault-aware Network-on-Chip Mapping Algorithms

Posted on:2017-04-18Degree:MasterType:Thesis
Country:ChinaCandidate:Z LuFull Text:PDF
GTID:2308330485484461Subject:Instrument Science and Technology
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As the time went by, the integrated circuit technology and the chip integration have been greatly developed. Thus the disadvantages of traditional bus based SoC become much more obvious, and NoC is then proposed and developed. Among this, higher demands are put forward to the performance of NoC by application requirements, which act as the core power of NoC and lead to the larger scale of NoC. But due to the feature size decreases to a certain range, power dissipation density within the chip increases and chip area limitation, the defects within the chip gradually increased, which affects system performance and reliability seriously. Therefore, it is of no delay to handle the fault-aware resource management scheme design in NoC. Thus we first put the emphasis on NoC fault modeling and the corresponding works based on the NoC platform in chapter 2; then due to the task management problems meet the multi-objectives optimal such as fault, performance and power dissipation, we proposed a fault-tolerant NoC task mapping algorithm based on fault model in chapter 3, and a fault-aware low power-dissipation dynamic NoC task mapping algorithm in chapter 4 respectively.Firstly, based on the analysis of NoC fault principle and the improvement of NoC lifecycle fault model, we established three types of router fault models: CornerR, SideR and MiddleR based on NoC topology structure, and gave a further classified study about the number and location of fault modes. Meanwhile, two types of link failure: horizontal versus vertical are also put forward by this paper. Directing at all the fault models, we combined models with specific NoC task mapping problem for detailed analysis.Secondly, based on the analysis of fault-aware in NoC fault-tolerant methods and the establishment of mapping platform as well as mapping algorithm performance assessment system, we proposed a fault-tolerant NoC task mapping algorithm FMA to tolerate three router and two link fault models. More specifically, we proposed a multi-priority optimized task scheduling algorithm based on breadth-first traversal, aiming at optimized the network communication performance in the pre-mapping stage. Then we designed a first node selection optimal method with considering the fault condition of neighboring nodes to optimize the mapping region selection. At last by avoiding fault nodes in task mapping process targeted to realize the fault tolerance in NoC platform.Thirdly, based on defect analysis of existing task mapping algorithms, we proposed a novel fault model based on spare core technology, and accompanied with the multi-objectives optimal such as fault, power dissipation and performance, we proposed a fault-aware low power-dissipation dynamic NoC task mapping algorithm FLDMA. More specifically, the minimum mapping area selection method is present in this paper to reduce the network congestion and improve the NoC communication performance, and after pre-designing with first-node optimal strategy and considering the failure rate to optimize the spare core numbers and locations, we began mapping process. With the real-time system status awareness, dynamic spare core setting through fault nodes status, and run-time task migration of this mapping scheme, we can largely reduce the total communication dissipation and the fault effect without disturbing the running applications in NoC.Finally, a NoC simulation platform is built to evaluate the proposed task mapping algorithm and the designed task mapping schemes. The results showed that under different fault models, our state-of-the-art FMA algorithm contrasted with the optimal fault-tolerant task mapping algorithm, achieved improvement up to 19.8% in average network delay, and optimization nearly 27.7% in network throughput. The results show that our proposed FMA algorithm own a better fault-tolerant and NoC optimal ability. At the same time about the state-of-the-art FLDMA algorithm proposed in chapter 4 compared with the optimal fault-aware task mapping algorithm, the AWMD value significantly reduced nearly 11.2%, achieved optimization nearly 5.8% of average network delay, also obtained a nearly 5.1% network throughput promotion, and the energy efficiency rate of NoC got nearly 1.32% increases overall. Aforementioned data analyses show that FLDMA algorithm get a better performance improvement, realize the multi-objectives optimal, and totally enhance the NoC communication performance.
Keywords/Search Tags:network on chip(NoC), fault-aware, task mapping, multi-objective optimal, PopNet
PDF Full Text Request
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