Research And Implementation Of Polyphase Filter Structure Based On FPGA

The Central idea of Software Defined Radio (SDR) is to establish a open, standard and modular universal hardware platform where the A/D converter is moved as closed as possible to antenna and all of the communication functions are realized by software.Decimator is a key module of Software Defined Radio. Through decimating and filtering, it slows down the signal rate to meet the requirements of following modules. Decimating in time domain causes signal frequency spread and alias. Therefore, anti-alias digital filters are required. And their performance determines the effect of decimator.This dissertation introduces basic theories and architectures of decimator, improving its original structure and giving its polyphase filter architecture. This structure implements first decimating and then filtering, reducing requirements of the operation speed of the filter.A method to implement filter part using FIR filter is applied by this paper, a scheme of hardware implementation is worked out using distributed arithmetic. As the scale of the LUT and the speed of the working in the distributed arithmetic algorithm are so large and slow, the discussion of optimization is carried on, then serial and parallel structures of the distributed arithmetic are introduced and compared.From the clew of implementing a hierarchical and modular design, the hardware design of all functional modules is described and polyphase filter architecture system is designed with the VHDL design methods in the thesis. The design is adopted to the Virtex-2 Pro serials device, with Matlab and other software tools. The simulation result shows that not only dose the amount of resources utility decrease but also the speed of working improves by using polyphase structure and distributed arithmetic, satisfying the requirements of signal real-time processing.