Research And Design On All-digital Syntheszable Low Power Clock Generators

The all-digital synthesizable clock generator has the advantages of low power consumption,small chip area and high portability in different technique process compared to conventional analog clock generators.With the rapid development of modern communication technology,the application of low-power and small-area integrated circuits is becoming more common.A clock generator with dynamic frequency-adjusted output can reduce power consumption of the circuit system under different workloads and extend the working time.At the same time,the all-digital synthesizable circuit design can be quickly transplanted under different technique process without the need for re-customization.Therefore,this paper selects an all-digital synthesizable clock generator for research and design implementation.This paper first proposes a new core frequency oscillation module.Based on the original ring oscillator chain,the delay unit bypass function is added,and the number of delay unit stages is available for selection,making the output frequency range wider.For the failure situation of a delay unit in the oscillation loop,by bypassing the delay unit,the normal operation of the clock generator can be achieved and the overall robustness of the system can be improved;in addition,when an even array delay unit is used,The frequency coarse adjustment module can be used as a delay chain of a delay locked loop to provide a multi-phase synchronous signal output with reference clock;also,the delay unit corresponding to the delay locked loop can be optimized.The control signal uses an odd array of delay elements to form a low-power phase-locked loop,providing a various design solution for the clock system.According to the new core frequency oscillation structure,this paper proposes the corresponding frequency search algorithm and two kinds of clock generator operation modes,which can improves the frequency locking speed and frequency output accuracy of an clock generator.In this paper,the new core frequency oscillation module and frequency search algorithm are put into two kinds of clock generator systems designs,including all-digital synthesizable multiplying delay locked loop and all-digital PLL.Two kinds of clock generators are built through the steps of modeling,RTL design,digital front-end simulation,back-end layout design and simulation.Using TSMC 65 nm all-digital technique process library,two all-digital synthesizable low-power clock generators were implemented.Among them,the all-digital multiplying delay-locked loop is tested on the TSMC and fabricated.The power consumption is only 0.9mW,the area is 0.018mm2,and the frequency output range is from 250 Mhz to 1.38 Ghz.The second clock generator,the all-digital synthesizable phase-locked loop chip occupies an area of 0.012mm2.Since the power consumption is specially optimized,the system power consumption is only 0.76 mW,so it can be well applied in low power system design.Both clock generators are implemented through standard digital chip design flow,which meets the design requirements for all-digital synthesizable low-power clock generators.