A Research Of Frequency Synthesizer For RFSOC

As a frequency synthesizer(FS),PLL is widely used in digital systems and analog systems.The frequency of the digital circuit is beyond 100 MHz with the development of electronic technology,and the main frequency of the kernel of a handset is more than 1.5GHz.In analog communication,high frequency carrier is more inevitable.The frequency of a crystal oscillator is difficult to reach the GHz level,although it can produce a frequency signal with high phase noise,and the higher the frequency,the worse the crystal conformance.So now the frequency of the GHz is usually produced by a low frequency clock with high quality and a frequency synthesizer.The low frequency signals are usually produced by DCXO,TCXO and other high quality crystal oscillators.The high frequency clock or carrier is generated by a phase-locked loop(PLL)that composed by voltage controlled oscillator(VCO)and other circuits.This paper provides a 5.7~ 6 GHz PLL design with the background of the 5.8GHz electronic toll collection system(ETCs).The article mainly discusses the following points in PLL Technology:1.Low reference-spur and phase noise: In this paper,the working principle of the PLL is analyzed,and a method to reduce the reference-spur and phase noise of PLL is proposed by reducing the mismatch current of charge pump,controlling the reset delay time of PFD,and using a smaller KVCO.2.Realization of fractional frequency divider:In order to meet the needs of the ETC system,the divider of this design is a fractional frequency division structure.So this paper analyses the corresponding multimode frequency divider and its corresponding sigma-delta modulator.3.Implementation an automatic frequency calibration(AFC)algorithm of multi tuning range PLL:In order to cover the entire output frequency range,the voltage controlled oscillator in this paper uses multiple capacitance arrays to realize the wide frequency output range.In order to achieve the accurate setting of the control word of the capacitive array before each lock,a common AFC algorithm is given.4.The PLL is designed and taped out in 130 nm CMOS process,and we have provided the detailed test results at the end.This PLL uses a 32.768 MHz reference frequency,the chip test results show that the frequency tuning range is 5.7~ 6 GHz,and the reference-spur is-68 dB.Compared with another method,this work's reference-spur is improved by 18 d Bc.The phase noise is-109dBc/Hz at 1MHz offset and-135dBc/Hz at 10 MHz offset in 5.835 GHz output.The power consumption of PLL is 12.1m W under the 1.5V power supply voltage.