Research On Key Technology Of RS Codec Used In Power Line Communication System

Because of the outstanding ability of RS code error correction and the highest coding efficiency in linear code,it makes RS code important in error correction code and is widely used in various fields.The research on RS codec is becoming more and more important as people continue to demand data transmission in power line communication system with high efficiency and high reliability.In this paper,the use of hardware logic design makes encoding and decoding of the RS code which is used in power line communication system achieved.Begin with the theory of channel coding,this paper introduces the knowledge of the most basic finite field theory in RS codec,and then focuses on introducing the algorithm and design of RS codec.In view of the finite field multiplier used in the RS codec frequently,this paper designs a general finite field multiplier,and its structure is regular,easy to be expanded and easy to be implemented by VLSI.Based on the pipeline structure,the Verilog hardware description language is used to realize the every module and the whole of RS(240,224)decoder,and the hardware logic design of RS(240,224)decoder is verified by FPGA.The module of solving critical equations is the most critical and core module of the entire RS decoder.Based on today's most mainstream RiBM iterative algorithm,this paper proposes a new algorithm to solve the key equation,namely FiBM iterative algorithm,by optimizing and improving.The algorithm achieves an effective breakthrough in hardware cost and does not increase power consumption,resulting in a reduction in the hardware footprint of the RS decoder without sacrificing throughput and decoding speed,resulting in a significant reduction in cost.At present,PLC is developing in the direction of high reliability and high accuracy.It is expected that this research can meet the needs of this development,and RS codec is getting more and more attention in PLC.