Research And Implementation On Digital Fountain Coder And Decoder

When we carry on data communication like the Internet which is based on erasure channel model, traditional transport protocols or coding scheme shows the serious deficiencies, large time delay, low channel utilization rate, serious wasting of resources and so on. We need a new way of coding to adapt to the current needs. Digital fountain code is developed based on the above reasons.Because of the incomparable advantages in the channel model, fountain codes have been widely studied and achieved certain results. Digital fountain code has no specific rate, no feedback channel, high resource utilization, low complexity, and adaptive multi user scenarios. It is precisely because of these excellent features that the digital fountain code obtained more attention and development.In this paper, we provide the important significance of the study of digital fountain codes, and give its development history and research status at home and abroad. The basic principles of digital fountain codes are given, including the type of encoding and decoding scheme, the degree distribution function, and the encoding and decoding algorithm.In the coding process, the phenomenon of repeated selection in LRLTC algorithm is introduced, and its specific performance and algorithm principle are introduced. Based on this, this paper designs several kinds of feasible improvement scheme, improved algorithm flow and specific details of the scheme, which can effectively solve the repeated selection phenomenon, fundamentally put an end to the occurrence of the phenomenon, and improve the performance of coding and decoding. At last, the simulation curves are given, which verify the feasibility of the improved algorithm.Finally, we completed the hardware implementation of the coding and decoding of digital fountain codes on the ARM9 S3C2440 A platform. First of all, the paper analyzes several algorithms used in the process of encoding and decoding, and then provides the details of the design of the overall framework of the system and each module. With hardware implementation we verified the performance of our improved LRLTC algorithm, and provided the simulation curve to verify by the actual performance of the algorithm, which effectively was for our conclusion.