Research On The Architecture Of JPEG2000 And The Hardware Implementation Of The MQ Coder In EBCOT

JPEG2000 is a new still image compression standard. Because of its distinguished compression performance and good flexibility, JPEG2000 is regarded to be very useful in various fields.This work does a study and research on the core algorithm and architecture of JPEG2000, especially focus on the MQ coder of its core coder named Embedded Block Coding with Optimized Truncation (EBCOT). By analyzing the algorithm and software implementation, it is found that the algorithm of MQ coder has a great perplexity which can not be implemented by software efficiently. In order to improve the coder's efficiency, hardware accelerator should be used.This work presents two architectures for the MQ coder to adapt to the pass-parallel bit-plane coding EBCOT : one is based on four-level pipeline and the other is a coder which can codes two bits per clock cycle. A software-hardware co-verification method is utilized to prove the designs'function and both designs have passed the tests. What's more, the speed is enhanced greatly by the hardware designs which can satisfy the demands of the pass-parallel bit-plane coding EBCOT. At last a comparison is made between the two architectures on speed, area and power consumption. Their strong points and weak points are worked out. The architecture based on four-level pipeline has a smaller area and lower power consumption, but its speed is lower as well. In contrast, the multi-bit coder's speed is higher at the cost of larger area and power consumption. In application, the architectures should be chosen according to the practical situations.