Research On Parallel Processing Architecture For Block Cipher Based On Stream Architecture

The diversification of block cipher algorithm and its application scenarios requires that cryptographic chip can implement a variety of block cipher algorithms efficiently and flexiblely.Therefore,the efficient and flexible implementation of block cipher becomes a hot research area in cryptographic implementation.Combined parallel computing and reconfigurable computing,the stream processing characteristics and parallelism of block cipher are systematically studied,stream architecture-based reconfigurable block ciper parallel processing architecture(SRBPA)is designed,and the method of block cipher parallel implementation based on software pipelining is proposed in this thesis.The main works and research creations are as the following:To develop the parallelism of block cipher absolutely,its parallelism is divided into four dimensions of parallelism(FDP)according to the perspective of the development means of parallelism.After deriving the speedup of developing each dimension of parallelism,the four dimensions of parallel processing model for block cipher(FDPM)based on Amdahl's law is put forward.The development priority of FDP is summarized by analyzing algorithm parameter,parallel parameter,etc.Moreover,the principle of block cipher parallel processing architecture design and algorithm parallel implementation that provides theoretical foundation and guidance for architecture design and algorithm mapping is further proposed.With FDPM as theory basis,the architecture of SRBPA is designed and implemented.Focusing on devising the structure of reconfigurable parallel processing cluster(RPC),several critical components such as reconfigurable parallel processing unit(RPU),distributed clustered register(DCR),reconfigurable distribution network,key scratch pad(KSP)and so on are designed.Furthermore,expanding within cluster,expanding between clusters and multi-core expanding are studied.Above-mentioned expansibilities make SRBPA have favourable expansion capability of function and performance.To shorten the width of instruction and decrease the code size of instruction set,the kernel level instruction set based on recongifurable very large instruction word(VLIW)is excogitated.After designing operation instruction,configuration instruction and hardware pipelining,reconfigurable VLIW technology which contains reconfigurable generation algorithm and reconfigurable distribution network is invented to dispatch instructions.In addition,the method of software pipelining that provides an important technological way for algorithm parallel implementation is proposed,and then the theory of this method and the collaborative executing mechanism between software pipelining and hardware pipelining are described in detail.The verification platform for the prototype of SRBPA is set up,and several block cipher algorithms such as AES-128,SM4,IDEA,DES,Camellia and RC6 are mapped,simulated and evaluated in serial working mode and parallel working mode.Moreover,the prototype is implemented in 65 nm CMOS process.The results show that the proposed architecture that is small area,high performance,high area efficiency and high utilization rate of functional units can satisfy the efficiency and flexibility of block cipher algorithms through parallelism development and reconfigurable design.