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Research On Reconfiguration Key Technology Of Block Cipher

Posted on:2018-11-29Degree:MasterType:Thesis
Country:ChinaCandidate:Y H ChenFull Text:PDF
GTID:2348330563951210Subject:Computer Science and Technology
Abstract/Summary:PDF Full Text Request
The reconfigurable technique of cryptographic algorithm allows the implementations to achieve an effective compromise in computational performance and flexibility,thus greatly improves the flexibility,security and efficiency of the whole information security system.In the field of reconfiguration of block ciphers,the existing research mainly focuses on the special reconfiguration between block ciphers and static general reconfiguration.There is still a lack of research on the reconciliation of cross-algorithm types in dedicated reconfigurable,dynamic general reconfiguration,and assessment of the reconfiguration in information security systems.In view of the above problems,this paper studies the reconfiguration key technology of block cipher,and the main work includes:1.In terms of dedicated reconfiguration of block ciphers,a reconfigurable model DPRM based on double pipeline for block cipher and stream cipher is proposed.The structural features and operational characteristics of the block cipher and stream cipher are summarized,the possibility of reconfiguration is discussed for specifications from specifications and parameters,the reconfigurable shift register and the reconfigurable S-box are dug as reconfigurable units and the reconfiguration model DPRM is proposed.In this model,outer and inner double pipeline is adopted to realize block cipher.The outer pipeline level is determined by the relative size of the two types of S-boxes,and the inner pipeline level is determined by the S-box layer of block cipher.The reconfiguration of the shift register is achieved by adding the mux at the front of the register,and the reconfiguration of the S-box is realized by using the paging RAM.Based on DPRM,a reconfigurable implementation method is designed for DES and ZUC.The feasibility and efficiency of the model are verified by experiments.2.In terms of general reconfiguration of block ciphers,aiming at the temporal partitioning problem of block cipher under non-feedback pipeline mode in dynamic general reconfigurable system,the optimal target and the corresponding priority are given,and a new method based on critical path depth-first searching and backtracking method CPDSB is proposed.The algorithm uses the hierarchical method based on ALAP scheduling to solve the problem of how to determine the critical path of the data flow diagram.By establishing and updating ready node list in real time,the possibility of deadlock is eliminated,which provides the sufficient condition for the full utilization of the hardware resources.Through the overall judgment of the brothers cluster,the algorithm solves the problem of choosing the search starting point.Using the depth-first search algorithm based on memory backtracking ensures that sufficient depth search can be performed along critical paths.Finally,the validity of the algorithm is verified bypartitioning four block ciphers.3.Aiming at the combination process from reconfigurable cryptographic operator to block cipher in information security system,a comprehensive evaluation method of operator combination quality based on aggregate index calculation is proposed.Aiming at the problem that the data flow diagram is not easy to describe the machine,the formal description method of process algebra Pi calculus is proposed to describe the combinatorial process.Combining with the reconfiguration feature of the operator and the characteristics of information security system,the hardware and software indexes are considered,and a five-dimensional model is proposed.On the basis of Pi calculus,the rules of aggregate calculation are given.In order to solve the problem of weight of different indexes in comprehensive evaluation,considering user's demand and preference,the quantitative weight of each index is calculated by fuzzy quantization method.4.For the general reconfigurable processor GRe P development platform,the structure of AES is optimized,and an efficient implementation scheme is proposed.In the GRe P-oriented optimization design,256 × 32 bit lookup table is adopted to merge substitute transformation and column mixed operation.In the GRe P-based mapping implementation,the computational overhead and configuration overhead are reduced by parallel and pipeline,and communication overhead is reduced by using local registers to store data and rational layout of PEs.Finally,the experiment is used to verify the efficiency of the scheme.
Keywords/Search Tags:block cipher, reconfigurable, double pipeline, temporal partitioning, general reconfigurable processor
PDF Full Text Request
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