Design And Implementation Of Reconfigurable Architecture For Stream Cipher Algorithm

In recent years,the scale of data has grown rapidly,and the status of information security has become increasingly prominent.Stream cipher plays an important role as an encryption system with good confidentiality,fast encryption and decryption speed,which is often used in areas with high security requirements such as national defense and military.In order to ensure information security infrastructure services,the implementation carrier of stream cipher algorithms should balance the indicators such as flexibility,performance and security.Reconfigurable cryptographic processor can meet the requirements that an information security solution may contain multiple cryptographic algorithms while ensuring a certain processing speed,and the security is also guaranteed.This paper designs a reconfigurable architecture for stream cipher algorithms.The research mainly focuses on the following aspects:(1)The development process of stream cipher is reviewed,the design structures of stream cipher algorithms are analyzed,the building blocks in the design of stream cipher algorithms are summarized,and the design structures of stream cipher algorithms are classified based on these.According to the classification,the target stream cipher algorithms are selected,and the structure characteristics and data flow characteristics of the target stream cipher algorithms are studied.From the perspective of reconfigurable computing,the structure and operation of the target stream cipher algorithms are decomposed,and the common logics of the target stream cipher algorithms are extracted.(2)The key technologies of reconfigurable cryptographic processors,namely storage unit,reconstruction granularity,operation function,interconnection structure,and configuration information,are studied,and based on these as an entry point,the reconfigurable architecture for stream cipher algorithms is completed.Mainly research and design reconfigurable feedback shift register array,tap extraction structure,reconfigurable arithmetic unit array,feedback data selection module and configuration information.(3)The designed reconfigurable architecture is implemented.ZUC,Grain v1,and Cha Cha20 with different structures and high practical application value are selected,and the mapping scheme of three algorithms on the reconfigurable architecture is designed,and RTL code is written and the simulation verification is completed using Model Sim.The logic synthesis of the reconfigurable architecture is completed,and the performance indicators of three typical stream cipher algorithms implemented on this architecture are evaluated according to the results of the logic synthesis.Under the TSMC 55 nm process,the clock frequency of the reconfigurable architecture designed in this paper can reach 1000 MHz,and the area is 979 k GE.Compared with other current reconfigurable cryptographic processors that can support stream cipher algorithms,the implementation performance and area efficiency of stream cipher algorithms with larger operation granularity(such as ZUC,Cha Cha20 etc.)on the reconfigurable architecture designed in this paper are significantly improved,such as the throughput rate of ZUC increased by 2.5 to 10 times.Although the implementation performance of stream cipher algorithms with smaller operation granularity is relatively low,these three stream cipher algorithms with different structures can be supported on the reconfigurable architecture,which also shows that the flexibility of the architecture is relatively high.