The Resarch And Design On Two Dimension Instruction System For Reconfigurable Block Cipher Processor

Facing the power consumption challenge of the miniaturization mobile terminal, as well as the cryptographic performance challenge of the cloud computing and big data processing system, the reconfigurable block cipher coprocessor is pressed for improving the energy-efficiency. This paper proposes a high energy-efficient instruction set architecture for the reconfigurable block cipher coprocessor, which could flexibly realize much block cipher algorithms.Under analyzing the operation character of block ciphers, the structure character of some processor instruction set architecture and the power consumption character of current reconfigurable block cipher coprocessor, this paper builds the energy-efficiency model of reconfigurable block cipher processor, based on the energy-efficiency definition. Under the model analysis, we purposed the Two Dimension Instruction Set Architecture(TD-ISA) for the reconfigurable block cipher processor.Based on analyzing the three operation characters of block ciphers, this paper purposes the Round Instruction Execute Structure of TD-ISA because of the iteration operation character and the stream operation character of the block cipher. This paper also purposes the Overlying Parallel Operation Structure of TD-ISA because of the adjacent different basic operation characters of the block cipher.This paper designs the instruction structure, the operate class microinstruction set and the control class microinstruction set of TD-ISA for the reconfigurable block cipher. This paper designed the addressing mode and the register virtualization description method of the TD-ISA. Using the balanced binary tree, this paper codes the operate class microinstruction set and the control class microinstruction set, which reduces the instruction bit wide and the area of the instruction RAM.In order to improve the cryptographic processing performance of TD-ISA, this paper offers a block cipher programming principle and the AES program. Under the verification platform, the instruction verification results and the system verification results show that the design is correct.Compared with area, performance and energy-efficiency of the VLIW reconfigurable block cipher coprocessor, results are as follow.1) The processor area is smaller than the VLIW reconfigurable block cipher coprocessor; 2) The performance is the VLIW reconfigurable block cipher coprocessor’s 1.17~3.98 times for the common block cipher; 3) The energy-efficiency is the VLIW reconfigurable block cipher coprocessor’s 1.7~5.66 times for the common block cipher.Compared with performance of another cryptographic processors or coprocessors, the results show that the multitask performance is another single-core cryptographic processors or coprocessors’ 1.1~8.92 times and the other multi-core cryptographic processors or coprocessors’ 0.48~1.6 times.