The FPGA Design Of Time Scheduling High Performance FC-AE Card

Nowadays distributed networks have got lots of development,such as Avionics Electronic System,Vehicle Communication System.Accompanied with some new requirements like accuracy and determinacy of network system,time trigger communication strategy has been invented and developed.This thesis compares FC network with Ethernet network firstly,and then studies the accuracy in FC network by analyzing TTE network.Considering the few researches of time trigger area on FC networks,this paper decides to choose time trigger on FC networks as the main component.The most important aspect in TTE is the invention of Time Trigger Strategy based on IEEE1588/AS6802 synchronization protocols.With Time Trigger Strategy using in Ethernet,the traditional network can be improved from the old event triggered to the new accurate time triggered.Under the same synchronization rules,all points run in the united time strategy,in this way to avoid the conflicts that may happen in the old networks.As for TTE there are IEEE1588 and AS6802 standard time synchronizing protocols,while there is no guide line standard on FC networks.Based on FC basic communication protocol,which uses primitives to keep the channel in active mode,this thesis creates a new time synchronization method in FC environment,uses time primitives in FC standard protocol to transfer clock information in 100 ns precision.Further more,this thesis creates two new primitives to transfer identification information of network device,extending the original FC protocol communication components.With this new method,the whole FC network ports can be synchronized in very short time,while there is no extra cost on the original bandwidth.There're 3 parts included.First part is the realization of FC bottom level protocols,like FC-0/1/2.Second part is about the clock synchronization mentioned above.Third part is a 4-lane PCIe 1.0 DMA design and realization.Due to the large programmable logic resources,strong reliability,short design period,this paper decides to use Xilinx FPGA as the design platform to realize the 3 parts.Firstly the Modelsim simulation tool will be used to test the RTL behavious of each module,make the board test.The test uses software and hardware combination methods,with the TTFC applications together to finish the board tests of all functions.