Design Of Single-phase Phase-locked Loop Under Distorted Grid Conditions

Phase-locked Loop(PLL)is the key technology of grid synchronization.In view of the poor harmonic rejection,the low anti-DC ability and the slow dynamic response in Second-order Generalized Integrator(SOGI)-based PLL,a novel cascaded SOGI-PLL(CSOGI-PLL)is proposed in this paper.In order to improve the filtering abilities of DC components and harmonics in utility voltage,a cascaded SOGI structure is adopted.And a parallel frequency detecting method is used to track the frequency variation of utility voltage.Unlike previous methods,it avoids extra negative feedback loop.Thus,CSOGI-PLL can obtain a greater bandwidth,an improved dynamic response and an enhanced stability under DC offsets,harmonics and frequency-varying conditions.On the other hand,CSOGI-PLL belongs to a digital PLL.It uses a Coordinate Rotation Digital Computer(CORDIC)alogrithm to detect phase error and a Direct Digital Synthesizer(DDS)to realize Voltage Controlled Oscillation.So CSOGI-PLL can be easily implemented on Field Programmable Gate Array(FPGA),which is also very suitable for low-cost chip manufacturing.Moreover,the implementation of PLL on FPGA can get a higher sampling frequency than DSP,resulting in better response speed and phase-locking accuracy.CSOGI-PLL is designed and coded using Verilog and finally implemented on a Nexys4 DDRTM FPGA Board from Xilinx.The development tool uses Xinlinx ISE.And experiments under various distorted grid conditions,including voltage dag,phase jump,frequency step,DC offset,harmonic distortion and combined disturbances,are done to verify the effectiveness and robustness of CSOGI-PLL.Experimental results are measured by the oscilloscope.The results prove that CSOGI-PLL possesses sufficient rejection capabilities of DC offsets and harmonics with the THD of 8.12%to obtain good steady-state accuracy and meet the IEEE C37.118 standand(the maximum phase error must below 0.57°).It also has a fast dynamic response and the settling time is shortened to 39ms under distorted grid voltage conditions.Particularly under frequency step of +5th,the settling time(27ms)is reduced by 2 to 3 times than other existing PLLs,and the overshoot is also smaller.