Research And Design Of A DSP Interrupt System

Compared with microprocessors,DSP chips have been widely used in the highreal-time demand of occasions because of their high computing speed.With the rapid increase of information,the DSP of status is becoming more and more obvious.This research topic comes from an industrial control DSP chip with rich peripheral resources.In order to meet the needs of a large number of peripheral interrupts,a three level interrupt system with two level vectors is proposed.Three-level tree structure can meet the requirements of many number of interruptions,two-level vector respectively as CPU interrupt request and peripheral interrupt request "identity card”,interrupt transfer through hardware and software combined with the completion of operation.The interruption system program,while taking into account the speed,but also reduces the hardware complexity.And the flexibility of the interrupt is very strong because the software takes on most of the interrupt transfer efforts.The DSP kernel uses a multistage pipeline design that interrupts the entire'production line' when an interrupt occurs.Compromise to consider the efficiency of interruption,the complexity of the kernel design and other factors after the precise interrupt mode is adopted.The method will discard all the instructions that have not been executed in the pipeline during the interruption,so there is no need to wait and respond immediately.The "interrupt field" that records the CPU operating status is saved by software.The above methods improve the outage efficiency and flexibility,and reduce the complexity of kernel design.The interrupt hardware is based on the Verilog hardware description language,and adopts the top-down,multi-level and multi module full synchronous circuit design.The DSP-level simulation of the design is carried out by NC-Verilog,through the simulation of non-blocking interrupt and blocking interrupt at the same level and different levels of interrupt.The simulation results show that the design has reached the functional requirements given by the scheme.The results of the DSP chip samples show the feasibility and correctness of the design.