Design And Verification Of X Microprocessor's Programmable Interrupt Control System

X microprocessor is a complex and powerful one. It adopts a series of new technologies, such as Dual-Issue superscalar, Dynamic Branch Prediction, Pipelined Floating-Point Unit, Bus cycle pipelining, Advanced Programmable Interrupt Controller (APIC) system. It not only can efficiently process Local Interrupt and System Interrupt in single processor system, but also it can process the inter-processor interrupt among multiprocessors.The APIC system is organized as three parts : Local APIC, I/O APIC and APIC bus. This thesis is mainly in order to design the Local APIC , which is applied to the X microprocessor (we call it as "XL-APIC" at the following parts). Firstly, we have researched the developing of the interrupt system, analyzed all kinds of interrupt systems at different phases, we also have learned the status and tasks of APIC in the interrupt system. Seqondly, we emphasized on the architecture and working methods of Pentium processor's APIC system, and we analyzed the limitation of the APIC at the high performance microprocessors, also we introduced the Streamlined Advanced Programmable Interrupt Controller (SAPIC) system and its attribute about architecture and performance. At last, we have realized all kinds of functions during the designing of the XL-APIC. According to the attribute of the X microprocessor, we optimized some logic module. Such as register file, timer/counter. In order to ensure correction of the design, XL-APIC adopts the down-up simulation verification strategy. It has divided three levels: sub-module level, module level, and system level. At every level, we do our best to simulate the function of the module.