Multi-cpu System Interrupt Mechanism

As we know, the enhancement of the CPU performance mainly depends on two mutual promoting factors which are the improvement of semiconductor craft and the development of CPU architectures. However, its frequency constrained by the semiconductor technics can hardly be increased since the beginnig of 21st century. To improve computer's performance, people turned to multi-processor architecture which has become the mainstream nowadays. Multi-processor technology, deploying more than one processor in a system, can achieve the goal of parallel processing by the collaboration work of those processors.In various multi-processor architectures, SMP is most widely used. SMP posses a strong ability of load-balancing and scheduling, thus, not only the system performance improvement can be assured, but also high reliability and stability can be gained. Meanwhile, SMP can be easily implemented on IA32 architecture. SMP's wide use, to some extent, is greatly attributed to the corresponding supports from both hardwares and softwares.This paper focuses on the analysis of how the interrupt mechanism is implemented in symmetrical multi-processing system and details its process from hardware to software. By reading it, you can get a clear picture of the specific routine of interrupt processing in SMP.In the end, the author describes some existing optimization technology for interrupt at length, further gives some new ideas and speculates the trends of researches in the future.