Research And Design Of High Performance DSP Interrupt System

With the development of electronic information industry, Digital Signal Processor(DSP)is widely used in military and civilian fields. Under the pressure of the market, DSP is movingtoward the target for high performance and low power consumption. Since the communicationbetween DSP core and peripherals relies on the interrupt system, the interrupt system hasbecome an important factor which will affect the performance of DSP.By analyzing the traditional structure of the interrupt systems and their workingprinciples, a high performance DSP interrupt system has been designed and realized. Thisinterrupt system has two interrupt processors, up to255priority levels. The interrupt serviceroutines can cross vector entries and group the interrupt priority in the interrupt vector table.Priority and arbitration time can be flexibly set in the real applications, making the interruptsource reasonable distribution and reducing the consumption of the DSP while handling theinterrupt process, besides it can improve the operation efficiency of the DSP core.In this thesis, the interrupt system is consisted of five units appling for service requests,service request nodes (SRNs), interrupt control units (ICU and PICU), two interruptarbitration buses and interrupt service providers. This interrupt system has two interruptservice providers: DSP and peripheral control processor (PCP), which handle the servicerequests together; peripherals that apply for interruption itself or software debug can be DSPor PCP; each peripheral is connected to one or more service request nodes to generateinterrupt service to the interrupt service provider, two arbitration buses connect the SRNs withthe interrupt control unit (ICU or PICU); the interrupt control unit is responsible forarbitration and determining the highest priority interrupt service request for DSP or PCP;finally the DSP or PCP respond and deal with the interruptions.In this thesis, by using hardware description language VHDL to describe RTL-level ofthe interrupt system, and the VCS simulation software by SYNOPSYS Company, we makefunctional verification of various interruptions in the system-level. The result shows that thedesigned interrupt system can meet the expected demand. In a high-frequency DSP system, ithelps saving2-6clock cycles and improves the efficiency of the system. This interrupt systemhas been successfully applied to a DSP chip and entered the market.