Design And Implementation Of AXI Bus System Based On Verification IP Verification Method

Nowadays,with the rapid development of IC manufacturing process,the design scale is getting bigger and more complex.The needs of today's society has forced designers to integrate more and more functions and modules into the same chip.The number of tasks to verify the design is exponential growing,and the difficulty has doubled.The IC verification trend is familiar with the knowledge of the premise of the circuit,and need more knowledge of the software and related skills.It requires greater reusability and the adequacy of verification,and the automation of verification platform.This thesis studies the design and implementation of AXI bus system based on Verification IP verification method.Taking the actual project as an example,this thesis studies how to use the hardware verification language,VIP tools and VMM verification method to build a reusable verification platform.This thesis analyzes the use of VMM verification methods for each component and the application of AXI-VIP(Advanced e Xtensible Interface-Verification IP)in the VMM verification environment in detail,and the benefits and practical implications of doing so.The VMM verification method is based on the hardware description language System Verilog.It has a perfect function library,and a Verification IP tool.Its function is relatively perfect,and reusable.The AXI bus is the core of the AMBA3.0.The AXI bus connects each module through the interconnection structure,and realizes the communication between different modules.The utility model improves the compatibility between different devices.It has advantages of smaller size and lower power consumption and better performance.According to the characteristics of AXI bus and the requirements of the IC design industry for the automation and reuse of the verification platform,this thesis proposes a hierarchical verification platform structure.It makes the direct excitation generation,the random excitation generation,the platform detection and coverage analysis mechanism.This method has the advantages of reusability and automation,which can shorten the design period and meet the requirements of the verification work.And its coverage is ideal.In this thesis,based on the in-depth analysis of VMM verification technology and the construction of VMM verification platform and the AXI bus signal collection and timing relationship,a power management chip is designed.In this thesis,the interconnection structure of shared address bus and multiple data bus is designed.And this thesis designed the arbiter adopts time division multiplexing and fixed priority arbitration method combining.And this thesis designed decoders for read and write address channel and write data channel and read data channel and write response channel.In this thesis,we mainly focus on the data length,size and burst read and write type,and use Verilog language to complete logic design for a pair of master and slave devices to read and write transactions.And build the VMM verification platform based on Verification IP tools to prepare for the verification work.According to the actual needs of the power management chip,the design of this thesis selects 64 bits data line,and the read and write address ID is 4 bits,and the burst read and write size is only using the lower two bits of the bus.Finally,this thesis extracts the function point and makes the verification scheme.In the verification,the code coverage and functional coverage reached 100%.This proves the completeness of the verification and the feasibility of the design.In this thesis,the VMM verification platform is built.And it provides reference for other design and verification work.