Research On TSVs Fault-tolerance And Memory Stack In 3D ICs

With the development of nanometer and sub nanometer manufacturing process,the performance of the Integrated Circuits(ICs)increased rapidly.The traditional chip design concept cannot meet the industrial requirements and the demands of the market,ICs industry has encountered serious challenges.Three-dimensional integrated circuits(3D ICs)has brought a new light for ICs industry.Compared with the traditional two-dimensional circuits,3D ICs has a higher integration and performance,it can also reduce the area and signal delay.However,the research of 3D ICs is still in the primary stage,both theoretical research and practical application are still facing many problems.Through Silicon Vias(TSVs),as the interconnection among the layers in 3D ICs,plays an important role in the whole system.Due to the limitations of the current manufacturing process,fault cannot be avoided.This paper presents a fault-tolerant scheme for TSVs on wire length-drive placement.Divide the circuit into several regions according to the number of signal TSVs,then add the redundant TSVs into each region to complete the repair.Comparing with existing TSVs fault-tolerance architecture,this scheme not only can decrease the number of redundant TSVs,but also decrease the complexity and increase the resume ratio.3D stacked memory has been a large-scale application in 3D ICs.Higher integration,less power consumption and stronger performance are competed as the focus of the chase by the major manufacturers.This paper proposed a sharing structure of adjacent redundancy across dies.Besides,based on the new redundancy sharing structure,a die-selection method stacking alternative memory layers with different number of faults was also presented.Experimental results show that the proposed method can significantly increase memory yield with relatively small area overhead of TSVs.