.0.5 Micron Mask Read-only Memory Technology Into Research And Yield Enhancement

The 0.5μm Mask ROM—Mask Read Only Memory process is new in our Fab. It is one type of MCU—Micro Controller Unit. The product can be used widely which has good marketing prospects. We mainly did the research on some critical layers to let the process meet the target.We also found out the root cause of low yield and impoved the yield to a higher level.This article is mainly about how to set up a new and stable process platform for Mask ROM products.It elaborates the method of the recipe tuning and low yield analysis.We first checked the mask related information. Engineers did DRC—Design Rule Check to confirm whether the size and profile of some patterns desighned was reasonable for manufacturing. We also need to confirm the bias between the mask and the layout and whether every mask is dark or clear.After that, the process flow should be set up. The process flow includes the stage name, the step ID, the step name, the reicpe name and the equipment group. So all the contents above should be determined correctly.The process of every step should be tuned and the reicpe name of every step should be created. We must check the CD—Critical Dimension of all kinds of lines(especially for critical layers, such as active area,gate poly, contact and metal lines etc.), the thickness of all kinds of films, the profile of the critical layers, the defect status and must tune the parameters of equipments such as particle, etching rate and etching uniformity etc.to determine the recipes.Then the process can meet the target.Then, this article enphasizes the root cause of "0" reading failure of CP—Chip Probe test and the solutions. We found the root cause of low yield by cross sectiong cutting,SEM check, TEM check and electrical parameter analysis and improved the yield from 22% to 96%.The root cause of low yield was found out by failure anaysis, cross section check by SEM—Scanning electron microscope and TEM—Transmission Electron Microscope, the analisys of correlation with the parameters of electrical characteristics and split experiments. At last the yield was improved to about 96% after some process tuning. The root cause of main yield loss is because bin9(bin means the different function of CP—Chip Probe test, bin9 means "0" read by 3.7V) and bin10(bin10 means "0" read by 1.7V) fail.The root cause of binlO failure was the As dose of BN+(BN+—Buried N+,it is the bit line which is the related circuit of "0" and "1" definition of Mask ROM) implant too high. So the resistance of BN+is lower. And there is high correlation between binlO with the resistance of BN+. The lower the resistance of BN+is, the more the bin10 will lose. The percentage of bin10 failure was decreased from 37% to 5% after the As dose was changed from 1×1015/cm2 to 8×1014/cm2, so the yield was improved from 22% to 55%.The bin9 failure was releate with Gate Poly Etch,Spacer Etch and Contact Etch. The effects of the 3 process caused the Si of SOURCE and DRAIN loss much more, so there would be more leakage between "N" type Si and "P" type substrate.It means there is leakage on the bit line. And the etching uniformity was not good, either. That is the root cause of bin9 failure. The percentage of bin9 failure was decreased from 32% to 10% after the 3 process fine tuning,so the yield was improved from 55% to 80%.Increasing the time (from 300s to 330s)of Vial etch can decrease bin9 and bin10 failure. Some via(1)s are opened because of less etching time. The percentage of bin9 can be decreased from 10% to 3% and bin10 can be decreased from 5% to 4%, so the yield can be improved from 80% to 90%.The yield can be improved to 96% by tuning device. The best condition is the Vt of NMOS is 0.85V and the Vt of PMOS is-0.85V.At last, the article introduced the the realibility qualifications of this product. We tested the following 5 items:HCI (Hot Carrier Injection), VTS(VT Stability), EM(Electromigration), GOI (Gate Oxide Integrity) and TDDB(Time Dependent Dielectric Breakdown) and every item passed.