| With the development of science and technology,the demand for wireless communication is becoming larger and larger.In wireless communication system,wireless channel,as the medium of signal transmission,plays an important role in the wireless communication system.To establish the optimal and most fitting the actual channel models,and to implement channel simulators based on these models,is an important part of the research and development of wireless communication system.Because of the high cost and the lack of flexibility,the professional channel simulators is restricting the efficiency of the development of the wireless communication.Compared to professional channel simulators,FPGA,that is inexpensive,can use the programming language to reset the internal resources flexibly.Therefore,the use of FPGA to achieve channel model,is an optimal selection of channel simulator.In this paper,the common channel models are simulated,and the improved scheme is proposed.Then,the model is implemented in FPGA,and software and ondoscope are used to verify the channel simulator.Firstly,the channel characteristics are simulated(such as scattering angle,spectrum and bit error rate),and some common channels are simulated and analyzed(such as Suzuki and COST 207).The improved model based on Jakes channel,reducing the number of random variables,reducing the complexity of the model is proposed.And the correlation and the envelope density of two order statistics,are more close to the theoretical model.Besides satisfying statistical characteristics,the improved model can save the hardware resources.In this paper,the Lutz dynamic model,which is often used in satellite channel,is simulated in the urban channel environment.And the model is extended by setting holding the distance as a variable.In addition,according to the COST 207 model,this paper proposes an improved model.The flat fading channel of the improved model are the Lutz dynamic channel and the Gauss Doppler channel.Finally,to implement the improved frequency selective channel,use the sub module design in FPGA.In this paper,the Virtex-5 series XC5VSX95 T of Xilinx company is the core processor,using the hardware programming language Verilog HDL to accomplish the design of FPGA channel simulator.For the above channel models,do test verification after he hardware implementation of the sub module.Modelsim is used to simulate each module in the hardware layer,and the simulated data is sampled into MATLAB to analyze the statistical characteristics.Finally,download the program to do the FPGA board level debugging.Use ondoscope to observe the waveform,and use Chipscope online test to verify the performance of the FPGA channel simulator. |
